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I initially ran into this doubt while trying to figure out whether a pipelined / super-scalar CPU is SISD, SIMD, MISD or MIMD. I did later read from Wikipedia (SISD article) that:

"According to Michael J. Flynn, SISD can have concurrent processing characteristics. Pipelined processors and superscalar processors are common examples found in most modern SISD computers."

Also from Wikipedia (MISD article):

"Pipeline architectures belong to this [MISD] type, though a purist might say that the data is different after processing by each stage in the pipeline."

So, is it correct to conclude that:

1) The requirement for 'Single Instruction Stream' processing is that there is only a single high-level thread of execution.

2) Just because instruction level parallelism in a thread is exploited, it cannot be considered 'Multiple Instruction Stream' processing.

What about the term 'Single Data Stream'?

Can someone say what the data stream for the following MIPS assembly code is:

  addi $s1,$s0,4
  lw $t0,0($s0)
  add $s2,$s0,$s1

Is it a 'Single Data Stream'? Does this situation change if the system exploits instruction-level parallelism?

Yuri
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Karthiksrndrn
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1 Answers1

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Think of a stream as an array of "stuff". If we are looking at SISD, then there is single array of instructions and single array of data. You pick an instruction form the instruction array and you operate on the data array. If we are going for SIMD, then there is only single array of instructions, but you get multiple data arrays. Therefore simply by looking at the instruction stream, as provided in your case, we cannot say whether its SISD or SIMD. If the underlying architecture has pipelines replicated, and each has a dedicated data stream (same as our data array), then the instruction given to that pipeline will operate on the dedicated data stream to that pipeline. All these pipelines has the everything replicated, registers etc. Therefore the addi $si,$s0,4 will be adding different values in each pipeline.

When we talk about ILP, we are basically looking for parallelism within a single thread and that's orthogonal to SISD or SIMD, because we want to exploit ILP in both cases.

Isuru H
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  • Are these instructions, in the same order as the program or are they in dynamic order or are they in some order which depends on the architecture? – Karthiksrndrn Jan 30 '17 at 17:35
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    You can think of instruction array as a thread. And they will be issued the same order they are defined in the thread. But in cases like SISD, or MIMD you can easily do optimisations like instruction reordering, branch prediction etc. This is a bit harder in SIMD, due the fact that data is coming from multiple streams. – Isuru H Jan 30 '17 at 18:10
  • So, is data array the collection of registers? – Karthiksrndrn Jan 31 '17 at 12:47
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    It can be, or it can be different portions of memory – Isuru H Jan 31 '17 at 14:12
  • So, Instruction Stream is basically a thread. Data stream refers to the operands (register or memory) of the instruction stream. So does that mean, in MISD different pipelines share the same set of registers? If, so wouldn't there be a conflict when data needs to be written, say to a register? – Karthiksrndrn Jan 31 '17 at 15:57
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    You are right to think like that, however to the best of my knowledge I do not know any working architecture configured exactly like MISD. Systolic arrays are often described as MISD, but in my understanding they are similar to a data flow machine where data flows through series of processing nodes where an operation is applied to the data at each node and I cannot 100% agree with they being classified as MISD simply because multiple operations are not applied on the data item at the same time. So in my view, MISD is simply there as a completion of parallel architecture matrix. – Isuru H Jan 31 '17 at 18:50
  • In MIMD systems like multi-core processors, even though different instructions streams are processed in different pipelines each with its own register set, aren't memory operands shared. So, isn't that a form of MISD? Or are we assuming that different threads use memory operands belonging to different virtual address spaces and hence such operands can be considered to be of different data streams? – Karthiksrndrn Feb 01 '17 at 06:12
  • In general, multi-core processors, operate on shared memory. There is a distinction how the shared memory is accessed. If a memory location is accessed concurrently, then it is similar to MISD. However when this happens, in the high level program, you are required to use locks, or barriers to maintain synchronization. These then translate into atomic operations in the hardware. Beauty of atomic operations is that, there can only be one successful operation to a given memory location at a given time. TBC – Isuru H Feb 01 '17 at 10:22