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In systemverilog there is no `if compiler directive. So the following lines are incorrect:

`define BITS 16

reg[`BITS-1:0] my_reg;

...
`if `BITS > 10
   my_reg[31] = 1'b0;
endif
...

Without `if there are warnings/errors.

How can I workaround or solve this?

dave_59
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betontalpfa
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2 Answers2

3

You can a procedural if statement

if (`BITS > 10)
      my_reg[31] = 1'b0;

and the compiler/synthesizer will optimize out a branching statement with a constant expression; meaning no extra logic gets created by the if statement.

To get around the out-of-bound message, you need a more complex expression (still a constant)

my_reg[(`BITS>31) ? 31 : 0] = 1'b0;
dave_59
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1800-2012 LRM, 22.5.1: "The directive `define creates a macro for text substitution." Eg.: 

`define D(x,y) initial $display("start", x, y, "end");

`D( "msg1" , "msg2" ) // expands to 'initial $display("start", "msg1", "msg2", "end");'

For numerical parameters you should use parameter / localparam depending on your needs.

anthrazithe
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