VHDL Warning: (vcom-1263) Configuration specification "all : bcd" applies to no component instantiation statements

Question

I have been stuck with this problem for a while. I would be really grateful if someone is able help. Have gone through most of the code repeatedly without any solution. There are sets of codes in use; this bcd counter is used further in the rest of my project. I have added the necessary codes below:

BCD counter for 1 digit:

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.NUMERIC_STD.ALL;
    USE WORK.mypackage_p.ALL;

    ENTITY bcd_e IS
    PORT(
    res_i, clk_i, enable_i, counter_res_i   : IN STD_LOGIC;
    bcd_o                   : OUT STD_LOGIC_VECTOR(bcd_width_c-1 DOWNTO 0);
    carry_o                 : OUT STD_LOGIC
    );
    END bcd_e;
    ARCHITECTURE bcd_a OF bcd_e IS

    SIGNAL count_s  : INTEGER RANGE bcd_cnt_c DOWNTO 0;

    BEGIN

    PROCESS(res_i, clk_i)
    BEGIN
    IF (res_i = '1') THEN
        count_s <= 0;
    ELSIF (clk_i = '1' AND clk_i'EVENT) THEN
        IF (enable_i = '1') THEN
            IF(count_s >= bcd_cnt_c) THEN
                count_s <= 0;
            ELSE
                count_s <= count_s + 1;
            END IF;
        END IF;
        IF (counter_res_i = '1') THEN
            count_s <= 0;
        END IF;
    END IF;
    END PROCESS;

    bcd_o <= STD_LOGIC_VECTOR(to_unsigned(count_s, bcd_width_c));
    carry_o <= '1' WHEN (count_s = bcd_cnt_c) ELSE '0';

    END bcd_a;

8 digit BCD using the above bcd counter to create 8 digits

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.NUMERIC_STD.ALL;
    USE WORK.mypackage_p.ALL;

    ENTITY bcd_8counter_e IS
    PORT(
    res_i, clk_i, enable_i, counter_res_i       : IN STD_LOGIC;
        bcd_array_o                     : OUT bcd_array_t
    );
    END bcd_8counter_e;

    ARCHITECTURE bcd_8counter_a OF bcd_8counter_e IS

    COMPONENT bcd   
    PORT(
        res_i, clk_i, enable_i, counter_res_i   : IN STD_LOGIC;
        bcd_o                   : OUT STD_LOGIC_VECTOR(bcd_width_c-1 DOWNTO 0);
        carry_o                 : OUT STD_LOGIC
    );
    END COMPONENT;

    SIGNAL bcd_array_s  : bcd_array_t;
    SIGNAL enable_s     : STD_LOGIC_VECTOR(no_of_digits_c-1 DOWNTO 0);
    SIGNAL carry_s  : STD_LOGIC_VECTOR(no_of_digits_c-1 DOWNTO 0);

    FOR ALL : bcd USE ENTITY WORK.bcd_e (bcd_a);

    BEGIN  

    carry_s(0) <= enable_i;

    gen_carry : FOR i IN 1 TO (no_of_digits_c-1) GENERATE
        carry_s(i) <= carry_s((i-1)) AND enable_s((i-1));
    END GENERATE gen_carry;

    gen_bcd : FOR i IN 0 TO (no_of_digits_c-1) GENERATE
    digitx : bcd PORT MAP(res_i, clk_i, carry_s(i), counter_res_i, bcd_array_s(i), enable_s(i));
    END GENERATE gen_bcd;

    bcd_array_o <= bcd_array_s

    END bcd_8counter_a;

My package file for the constants:

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.NUMERIC_STD.ALL;

    PACKAGE mypackage_p IS

    CONSTANT freq_20k_c         : INTEGER := 2500;
    CONSTANT bcd_cnt_c      : INTEGER := 9;
    CONSTANT bcd_width_c        : INTEGER := 4;
    CONSTANT no_of_digits_c     : INTEGER := 8;

    TYPE bcd_array_t IS ARRAY(7 DOWNTO 0) OF STD_LOGIC_VECTOR(3 DOWNTO 0);
    END PACKAGE;

I keep getting the following warning:

Warning: /home/stud/mr-131416/Desktop/VHDL_Project_Latest/src/bcd_counter8_a.vhd(15): (vcom-1263) Configuration specification "all : bcd" applies to no component instantiation statements.

The code does not pass test/simulation of a test-bench because of this warning. Help would be really appreciated.

Answer 1

It's a matter of scope. A component configuration configures a component instantiation. The generate statement produces a block statement (or nested block statements when a port map is supplied).

A block statement (for an internal or external block) use a block configuration which is only found in a configuration declaration.

Binding indications are not hierarchical, without the ability to reach down into a block to specify a component instantiation you can either use a configuration declaration or move the configuration specification:

    -- for all : bcd use entity work.bcd_e (bcd_a);

begin  

    carry_s(0) <= enable_i;

gen_carry : 
    for i in 1 to (no_of_digits_c-1) generate
        carry_s(i) <= carry_s((i-1)) and enable_s((i-1));
    end generate gen_carry;

gen_bcd : 
    for i in 0 to (no_of_digits_c-1) generate
        for all: bcd use entity work.bcd_e (bcd_a);
    begin

    digitx : bcd port map (res_i, clk_i, carry_s(i), 
                           counter_res_i, bcd_array_s(i), enable_s(i));
    end generate gen_bcd;

    bcd_array_o <= bcd_array_s;  -- CHANGED WAS MISSING SEMICOLON

end bcd_8counter_a;

Note the missing semicolon on the assignment statement for bcd_array_o has been added.

With these changes your design analyzes and elaborates without warnings.

You could note not all synthesis tools support configuration declarations while most support configuration specifications.

See IEEE Std 1076-2008 7.3 Configuration specification, 3.4 Configuration declarations, 3.4.2 Block configurations

The failure to simulate or synthesize would be because the distx component instantiations are unbound because there isn't a bcd entity found in the working directory.

Writing a simple testbench that does not invoke the synchronous reset, uses a clock with a 10 ns period and runs for 10 ms:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mypackage_p.all;

entity tb is
end entity;

architecture foo of tb is
    signal reset:       std_logic;          -- '1' for RESET
    signal clk:         std_logic := '0';
    signal en:          std_logic;          -- '1' for ENABLE
    signal syn_reset:   std_logic;          -- '1' for SYNCHRONOUS RESET
    signal bcd_array:   bcd_array_t;

begin
DUT:
    entity work.bcd_8counter_e
        port map (
            res_i => reset,
            clk_i => clk,
            enable_i => en,
            counter_res_i => syn_reset,
            bcd_array_o => bcd_array
        );
CLOCK:
    process
    begin
        wait for 5 ns;
        clk <= not clk;
        if now > 10 ms then
            wait;
        end if;
    end process;
STIMULI:
    process
    begin
        wait for 10 ns;
        reset <= '0';
        en  <= '0';
        syn_reset <= '0';
        wait for 10 ns;
        reset <= '1';
        wait for 20 ns;
        reset <= '0';
        wait for 20 ns;
        en <= '1';
        wait;
    end process;
end architecture;

Shows that the counter depends on enable and shows that the first 6 digits work: