Error (10663): Verilog HDL Port Connection error at DSD_Project.v(34): output or inout port "hit" must be connected to a structural net expression

Question

module DSD_Project(flag0, flag1, hit0, hit1,room_counter,someone_inRoom,someone_Spying,hit0_LED, hit1_LED,echo0_LED, echo1_LED, anti_theft_output,reset_Antitheft_output,echo0, echo1, CLOCK_50,anti_theft, reset_Antitheft);

    output reg hit0_LED = 1'b0;
    output reg hit1_LED = 1'b0;
    output reg echo0_LED = 1'b0;
    output reg echo1_LED = 1'b0;
    output reg flag0 = 1'b0;
    output reg flag1 = 1'b0;
    output reg hit0 = 1'b0;
    output reg hit1 = 1'b0;
    output reg room_counter = 1'b0;
    output reg someone_inRoom = 1'b0;
    output reg someone_Spying = 1'b0;
    output reg anti_theft_output = 1'b0;
    output reg reset_Antitheft_output = 1'b0;
    input echo0; // input_signal from the sensor 1
    input echo1;// input_signal from the sensor 2
    input CLOCK_50;
    input anti_theft ;   //= 1'b0; // switch button
    input reset_Antitheft; // = 1'b0; // push button

    sensor s1(hit0, echo0) ; // , CLOCK_50);
    sensor s2(hit1, echo1) ; // , CLOCK_50);

    always@(posedge CLOCK_50)
        begin           
            hit0_LED <= hit0;
            hit1_LED <= hit1;
             echo0_LED <= echo0;
             echo1_LED <= echo1;     
        end

    //anti_theft: seting and reseting the output 
    //always@(anti_theft)  //or reset_Antitheft)
        //begin
            //anti_theft_output <= anti_theft ;
            //reset_Antitheft_output <= reset_Antitheft ;
        //end

    always@(posedge hit0 or posedge hit1)
        begin     
            if (hit0 == 1 && hit1== 0)
                begin
                    flag0<= 1;
                    //flag1<= 0;
                    if(flag1==0)
                        begin
                            hit0=0;
                            room_counter <= room_counter +1 ;
                            someone_inRoom <=1 ;
                            if(anti_theft == 1)
                                someone_Spying <= 1;
                        end
                    else
                    flag1<=0;               
                end
         else
            begin
                if ((hit0 == 0) && (hit1 == 1))
            begin
                    //flag0<=0;
                    flag1<=1;
                    if(flag0 == 0)
                        begin
                            hit1=0;
                            room_counter <= room_counter -1 ;

                            if(room_counter==0)
                                begin
                                    someone_inRoom <=0 ;
                                end
                        end
                    else
                    flag0<=0;
            end
            end
     end 
     always@(reset_Antitheft)
     begin
     if( (anti_theft==1) && (someone_Spying == 1) )
        begin
            anti_theft_output <= 0 ;
            someone_Spying <= 0 ;
        end
     end 
endmodule


module sensor(hit, input_signal); //, CLOCK_50);

    input input_signal;   
    output reg hit = 1'b0; 
    //reg [25:0] clock_counter;

    always@(input_signal) // posedge CLOCK_50 ||
      begin
            //if (clock_counter == 8_000_000)   
                begin               
                    if (input_signal==1)
                        begin 
                            hit <= 1;                  
                        end
                    else
                        begin
                            hit <= 0;      
                        end         
                end
            //else
            //  clock_counter <= clock_counter+1;   
        end     
endmodule

ScreenShoot

Answer 1

As you would know, the problem is with the following lines:

sensor s1(hit0, echo0) ; // , CLOCK_50);
sensor s2(hit1, echo1) ; // , CLOCK_50);

In sensor, the first port, hit is a output. However, you're attempting to connect it to a reg, as you specified in the lines above:

output reg hit0 = 1'b0;
output reg hit1 = 1'b0;

You should use these signals as wires, not regs.