VHDL Syntax error with if then process

Question

library ieee;
use ieee.std_logic_1164.all;

entity basic_shift_register_with_multiple_taps is

    generic
    (
        DATA_WIDTH : natural := 8
    
    );

    port 
    (
        clk          : in std_logic;
        enable       : in std_logic;
        sr_one       : in std_logic_vector((DATA_WIDTH-1) downto 0);
        sr_two       : in std_logic_vector((DATA_WIDTH-1) downto 0);
        sr_out       : out std_logic_vector(2*(DATA_WIDTH-1) downto 0)
    );

end entity ;

architecture rtl of basic_shift_register_with_multiple_taps is

    
    signal sig_out  :std_logic_vector(2*(DATA_WIDTH-1) downto 0);
    variable count  : integer := 0;
    variable count1 : integer := 0;
    
begin
    
    process (clk,enable,sr_one,sr_two,sig_out)
    
    begin
    
        if(enable = '0' or count = 16) then 
            count := 0;
            count1 := 0;
        else if (clk'event and clk='1') then
            sig_out(count) <= sr_one(count1);
            
            count := count + 1;
        
        else --if (clk'event and clk='0') then--
            sig_out(count) <= sr_two(count1);
            count := count + 1;
            
        end if;
        
        count1 := count1 + 1;   
        
        
(54)    end process;

    sr_out <= sig_out;

(58) end rtl;

errors:

Error (10500): VHDL syntax error at teste.vhd(54) near text "process"; expecting "if"

Error (10500): VHDL syntax error at teste.vhd(58) near text "rtl"; expecting "if"

It's complaining about a missing "end if". My guess is you don't have a VHDL syntax guide handy so you guessed how o spell "elsif" and missed. — , Jan 10 '17 at 11:20

score 1 · Answer 1 · edited May 23 '17 at 12:01

Your problem is that your second if statement

if (clk'event and clk='1') then

has no end if associated with it. So, when the compiler gets to line 54, it encounters an end process before the end if it was expecting. Instead of this

if(enable = '0' or count = 16) then 
    count := 0;
    count1 := 0;
else if (clk'event and clk='1') then
    sig_out(count) <= sr_one(count1);

    count := count + 1;

else --if (clk'event and clk='0') then--
    sig_out(count) <= sr_two(count1);
    count := count + 1;

end if;

do this:

if(enable = '0' or count = 16) then 
    count := 0;
    count1 := 0;
else
    if (clk'event and clk='1') then
        sig_out(count) <= sr_one(count1);
        count := count + 1;
    else --if (clk'event and clk='0') then--
        sig_out(count) <= sr_two(count1);
        count := count + 1;
    end if;
end if;

However, if you are intending to synthesis this, your syntax error is the least of your worries. See this answer.

@MatheusSasso As I said, you need to look at [this answer](http://stackoverflow.com/questions/36539962/errorxst827-signal-count-cannot-be-synthesized-bad-synchronous-description/36543625#36543625). You have describe behaviour that is not synthesisable. A logic synthesiser's job is to think of a circuit that behaves like you code. It cannot do this. Nor can I. You have described behaviour that cannot be implemented using combinational logic and D-type flip-flops. The error messages in your other question tell you what this behaviour is. So, you need to change your code as in the link I posted. — Matthew Taylor, Jan 10 '17 at 14:35

VHDL Syntax error with if then process

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