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I am working on a project about a frequency-hopping tranceiver. I want to implement a phase lock loop on FPGA i.e. a digital PLL. I am multiplying the incoming signal with a certain frequency and passing it through a LPF. Now I give this low frequency to DDS. I want my DDS to work like a VCO and lock to incoming phase/frequency. How can I do that?

I also need to know that how the phase accumulator in a DDS works: how or what input they are getting to generate corresponding frequency?

Martin Thompson
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kamran zia
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1 Answers1

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The datasheets of the Xilinx DDS Compiler have some information about the theory of operation. You may want to have a look at them.

geschema
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