unexpected output from signal processing structure module

Question

Undertaking this problem i am getting an unexpected output of X (unknown value) from my Verilog code.

Would appreciate if someone could show me where i am going wrong, code is attached.

problem

module code

// Signal processing structure

module sps(in1,clk,rst,out1);

input clk,rst;
input signed [19:0] in1;
output reg signed [19:0] out1;


reg signed [19:0] w,w1;



always @(in1 or w or w1) begin
             w <= in1 + w1;
             out1 <= w + ~w1;
            end

always @(posedge clk) begin
    if(~rst) 
        w <= 0;
    else begin
        w1 <= w;
         end    
end 


        endmodule

testbench code

// test sps

module testSps;

reg clk,rst;

reg [19:0] in1;
wire [19:0] out1;


sps sps1(in1,clk,rst,out1);


initial
    begin
    rst = 0;
    clk = 0;
    in1 = 20'b0000000000000000001;
    #5 rst = 1;
    #50 $stop; 
    end

always      
    #5 clk = ~clk;





endmodule

thanks @toolic appreciate the response, could you provide an answer to the question specifying why this is the case? I would like this in order to understand more what is happening! — Eoghan_Mulcahy, Dec 07 '16 at 16:14

score 0 · Answer 1 · answered Dec 08 '16 at 02:39

Few observations in your design & testbench code.

You havent initialised the clk signal in the testbench. Please add clk = 0 in the starting of the initial block in your testbench.
The below always block looks self updating loop to me. Because w is there in the sensitivity list and also it is being updated in the block.
```
always @(in1 or w or w1) begin
  w <= in1 + w1;
  out1 <= w + ~w1;
end
```
w is driven through multiple always block. A net should be driven only through single always block. You can combine both always blocks to drive w as follow. May be you wanted to set w1 to 0 in the 2nd always block.

unexpected output from signal processing structure module

1 Answers1