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I've been digging for quite some time and always hit a brick wall, when I try to estimate the FLOPs of a MIPS64 CPU series, that I'm evaluating for an embedded design. Moreover I can't seem to find how many floating point operations this CPU can do per clock, per core, which is really frustrating, because otherwise I would've been able to calculate it myself. All I can find for any MIPS32/64 CPU is the DMIPS, which doesn't help me much, because I want to compare it towards other processors, most of which haven't run dhrystone and even if they did, I'm not entirely sure it'd make any sense to scale the one result towards the other.

Can anyone shed some light over how MIPS cpu cores handle float operations and in what amount of cycles? The MIPS64 CPU I'm looking at is quad-issue quad-threaded one, should the instruction issue tips the scale either way.

Thanks in advance!

Cheers,
vlex

vlex
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  • Isn't the MIPS32/64 just ISAs? Don't you need a specific model in mind? – Margaret Bloom Dec 01 '16 at 08:38
  • @MargaretBloom Well I was left with the impression that the MIPS32/64 are also CPU architectures, but if I got that one wrong, it explains why I can't find jack about them. The CPU, I'm digging about is NetLogic/Broadcom's XLP832 and is based on EC4400 cores. Hope that helps at least a bit. – vlex Dec 01 '16 at 08:54
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    This appears to be a question about "general computing hardware", rather than a programming question. Voting to close. – njuffa Dec 01 '16 at 14:09
  • MIPS is a CPU architecture, which has many different implementations. Floating point performance is implementation specific, and not specified in the architecture definition. You need to get the performance information from your processor vendor. – markgz Dec 01 '16 at 21:03
  • @markgz I agree that it's implementation specific, however for ARM A7 or A15, there's information how many NEON, or VFPv4 instructions they can compute pe clock, the same with different x86 architectures, or other RISC architectures. How comes I can't find jack for MIPS - it's really frustrating... – vlex Dec 01 '16 at 23:56
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    I believe that Broadcom has a MIPS architecture license, so only Broadcom knows what a Broadcom CPU can do. This is just like Apple's ARM implementations, where only Apple knows what they can do. – markgz Dec 02 '16 at 01:51

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