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I recently took a look at the config file of my ARM64 linux kernel and noticed that the following options are set :-

CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_VA_BITS_48=y
CONFIG_ARM64_VA_BITS=48

Looking at slide 8 here, I see that a 4KB page size and a 48 bit VA means that there are 4 levels of translation. So I look at the Aarch64 reference manual.

For convinience, I have uploaded a picture from page 1718 of the reference manual.

Translation

I can see that the index to the translation table at each level is 9 bits(except at the last level). As a result, the zero, first, and second translation table should be able to index 2^9 values.

My doubts are :-

  1. What is the size of each item inside the zero, first, second and third translation table?
  2. How did you obtain this information / arrive at this conclusion?

[EDIT] Correct the number of bits from 8 to 9.

Stoogy
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  • What does "the size of each item" mean? The size of a PTE? the size of a table? The amount of address space covered by an entry at each level (i.e. the block size)? Also, count again; it's not 8 bits per level. – Notlikethat Nov 30 '16 at 22:53
  • @Notlikethat Thanks. I have changed from 8 to 9 bits. Yes, I mean the size of each entry(PTE), at different translation table levels. –  Nov 30 '16 at 22:58
  • Given that you're quoting the architecture manual, you have read D5.3 and D5.4, right? Perhaps unsurprisingly, AArch64 PTEs are 64 bits. Sorry, but I'd file that under "trivially obvious". – Notlikethat Nov 30 '16 at 23:15
  • Thanks, if you can add that as an answer i can accept –  Nov 30 '16 at 23:43

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