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sometimes in UPPAAL I found an example for an integer variable taking two values like int x:=1-0, what does this exactly mean ? like x is taking first "1" then "0" or X is just an array of two values ?

Thank you

Hachani Ahmed
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  • There is no special meaning to such an expression: `1-0` simply evaluates to `1`. Perhaps you've seen an assignment expression `x:=1-x`, which would alternate between `0` and `1`. – mariusm Nov 30 '16 at 19:37
  • I found it in some code like in here http://www-soc.lip6.fr/~ema/valmem/valmem/vhdl2ta/circuits_studies/d_flip_flop/upl/delay1/d_flip_flop_param.ta and it make a difference , this is an example for a flip flop D , the signal D sometimes not only take ''1'' or ''0" at one time , but also D=1-0 or D=1-1 I was like not sure about this , and If I change it, it will make a difference in the behaviour – Hachani Ahmed Dec 01 '16 at 02:06
  • It looks like it has been generated. Do you have a smaller example where you can observe the difference in behavior? – mariusm Dec 01 '16 at 09:39
  • yes, I tried to build something similar starting from this example , I had a nand gate called "g1" that takes at one input a signal D and in the other input a clock ck , so in my UPPAAL model l_xo_g1 means the state of transition from 1 to 0 and l_x1_g1 transition from 0 to 1 ,l_f_g1 is the state where the signal os stable either 0 or 1, for example to get a 0 at the ourtput of the Nand gat I should have both input signal at "1" so my clock rising edge will be 1 and my D "1" , in the gard, If I write D=1 and ck=1 no transition happen , Unless I write D=1 and Ck=1-1 so it can work – Hachani Ahmed Dec 01 '16 at 17:31
  • ![D latch] (http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/ietron/dflipflop3.gif) see the first Nand Gate with D input and Clock Ck and this is a link for the Nand gate model https://drive.google.com/open?id=0B-7Y2O_twAG2VjdFTGxZWDhSTG8 (I couldn't post images directly) – Hachani Ahmed Dec 01 '16 at 17:38
  • Actually the models would be better than images -- I need to see how the tool interprets those expressions. – mariusm Dec 03 '16 at 01:29
  • this is the model of the first gate process Ass_g1() { state l_x0_g1 {x_g1 <= delta0_u_g1}, l_x1_g1 {x_g1 <= delta1_u_g1}, l_f_g1 {true}; init l_f_g1; trans l_x0_g1 -> l_f_g1 { guard x_g1 >= delta0_l_g1; sync g1_down!; assign g1 := 0; }, l_x1_g1 -> l_f_g1 { guard x_g1 >= delta1_l_g1; sync g1_up!; assign g1 := 1; }, l_f_g1 -> l_x1_g1 { guard d == 1-0 and ck== 1; sync d_down?; assign x_g1 := 0; }, – Hachani Ahmed Dec 03 '16 at 22:36
  • l_f_g1 -> l_x1_g1 { guard d == 1 and ck== 1-0; sync ck_down?; assign x_g1 := 0; }, l_f_g1 -> l_x0_g1 { guard d == 1-1 and ck== 1; sync d_up?; assign x_g1 := 0; }, l_f_g1 -> l_x0_g1 { guard d == 1 and ck== 1-1; sync ck_up?; assign x_g1 := 0; }; } – Hachani Ahmed Dec 03 '16 at 22:36

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