The signal _IBUF> is incomplete

Question

I am trying to write a VHDL module but I am having some input problems, here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;


entity binary_add is
    port( n1 : in std_logic_vector(3 downto 0);
    n2 : in std_logic_vector(3 downto 0);
    segments : out std_logic_vector(7 downto 0);
    DNout : out std_logic_vector(3 downto 0));

end binary_add;

architecture Behavioral of binary_add is
begin

DNout <= "1110";

process(n1, n2)

variable x: integer;


begin

x:= conv_integer(n1(3)&n1(2)&n1(1)&n1(0)) + conv_integer(n2(3)&n2(2)&n2(1)&n2(0));

if(x = "0") then

segments <= "10000001";

elsif(x = "1") then

segments <= "11001111";

else

segments <= "00000000";

end if;

end process;

end Behavioral;

I am getting these errors:

WARNING:PhysDesignRules:367 - The signal <n1<1>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <n1<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <n1<3>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <n2<1>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <n2<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <n2<3>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:Par:288 - The signal n1<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal n1<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal n1<3>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal n2<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal n2<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal n2<3>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

The errors seems complicated but actually it says, I think, cannot route the other 3 inputs of my n1 and n2 signals. I do not why this is happening but all I want to do is displaying summation of n1 and n2 signed numbers into 7-segment display. If anyone can help me to figure out this issue, I would really appreciate it.

score 3 · Accepted Answer · answered Nov 03 '10 at 13:48

First: Don't use std_logic_arith or std_logic_signed - I've written about why not. Second: you have created an asynchronous process, which is not great practise in FPGAs which are designed for use (and the tools expect you to use) in a synchronous fashion. Create a clock input and use it. You can do it asynchronously, but until you really know what you're doing, avoid it. Once you really know what you're doing, chances are you'll avoid it as well, because you understand how nasty it will be :)

I'd make my ports of signed type and use ieee.numeric_stdd.all;. Or even use the integer type on the input ports. If this is the top-level block, you'll need to put a wrapper around to take std_logic_vectors on the outermost pins, turn them into integers and feed them into the block you've written above:

n1 <= to_integer(signed(n1_pins));

Then you need to do something like this...

architecture Behavioral of binary_add is
begin
DNout <= "1110";
process(clk)
  variable x: integer;
begin
  x:= n1+n2;
  case x
    when 0 => segments <= "10000001";
    when 1 => segments <= "11001111";

etc

Or create a constant array to convert integer to 7-segment and do

segments <= int_to_7seg(x);

The signal _IBUF> is incomplete

1 Answers1