Vivado SoC Zynq: creating custom IP

Question

I'm trying to work on this Lab tutorial for creating custom IP in Vivado. Can anyone please explain me the meaning of the codes in page 6 step 1-3-9. I don't really get the meaning of those syntax.

Link: http://www.dc.uba.ar/materias/CoDisenio/2015/c2/descargas/lab3.pdf

Here is the code:

lab3_user_logic # (
.LED_WIDTH(LED_WIDTH)
)
U1(
.S_AXI_ACLK(S_AXI_ACLK) , 
.slv_reg_wren(slv_reg_wren) , 
.axi_awaddr(axi_awaddr[C_S_AXI_ADDR_WIDTH-1:ADDR_LSB]) ,
.S_AXI_WDATA(S_AXI_WDATA) , 
.S_AXI_ARESETN(S_AXI_ARESETN),
.LED(LED)
);

Thank you so much.

You're using a VHDL tag while your code snippet appears to be Verilog, — , Nov 25 '16 at 23:37
I have no knowledge about Verilog code. Can you please give me a brief explanation of what these codes mean? — Nguyễn Thanh Vũ, Dec 22 '16 at 22:01
You can download [IEEE Std 1800-2012](https://standards.ieee.org/getieee/1800/download/1800-2012.pdf) for your personal use without charge. See Annex A.4.1.1 Module instantiation explaining the syntax. The first part (**#(...)**) containing a parameter value assignment is the equivalent of a generic map. The second part is a hierarchical instance has a list of port connections with named port connections (like a VHDL port map aspect). Also see Clause 23 Modules and hierarchy, 23.3 Module instances (hierarchy). — , Dec 23 '16 at 09:56

score 0 · Answer 1 · answered May 11 '18 at 23:31

lab3_user_logic module is instantiated in the above code. The code segment between "# (" and ")" indicates the parameters set for this instance. The name U1 is the instance name. All the lines of code below it are the I/O signals(ports) of the module. They are either sampled/driven by signals they are connected to at the scope where U1 is present

Regards, Bharadwaj

Vivado SoC Zynq: creating custom IP

1 Answers1