I am working with the Zynq-7000 SoC - developing a dual core (CPU0, CPU1) application. I want to use the shared on-chip memory (OCM) with cache disabled for bidirectional data exchanging between the cores. My idea is to set the data sharing in the following manner:
typedef struct
{
uint8_t mstatus;
uint8_t[10] mdata;
} mailbox;
mailbox core0mbox;
mailbox core1mbox;
Structure mailbox
holds a buffer for storing the data (mdata
) and its status (mstatus
). The status may be equal to 0
or 1
(in general - a zero value indicates that the data has been processed by the receiver and new data may be written into the buffer; a non-zero value indicates that the data has not been processed by the receiver yet). There are two mailboxes - core0mbox
(stores the data received by core 0 from core 1) and core1mbox
(stores the data received by core 1 from core 0), both stored in the OCM.
When the core 0 wants to send the data, it polls the status flag core1mbox.mstatus
- if it is equal to zero, the core fills the buffer associated with
core1mbox
with data and then sets the flag associated withcore1mbox
to1
- if it has a non-zero value, the core cannot send the data
When the core 1 wants to send the data, it polls the status flag core0mbox.mstatus
- if it is equal to zero, the core fills the buffer associated with
core0mbox
with data and then sets the flag associated withcore0mbox
to1
- if it has a non-zero value, the core cannot send the data
The core 0 periodically polls the core0mbox.mstatus
- if it has a non-zero value, then the core 0 processes the data and after finishing it sets core0mbox.mstatus
to 0
.
The core 1 periodically polls the core1mbox.mstatus
- if it has a non-zero value, then the core 1 processes the data and after finishing it sets core1mbox.mstatus
to 0
.
My question is - could this scheme lead to an undetermined behavior of the system (e.g. data corruption) due to problems caused by the concurrent accesses? I know that this scheme could not work if the status flag could have more values (problems due to non-atomic write/read operation) or if there would be a larger number of cores in the system, but it seems to work well for the situation described.