/Entry in an UML state diagram with VHDL

Question

I'm implementing an UML state diagram with VHDL using case statement. do/ and exit state activities are easy to implement. However, does anyone know how to implement the entry state activity in an efficient way?

I thought of adding a flag to execute only one time or adding an extra state called name_entry before of name state. But I dislike these options...

It's hard to see what you want to do from what you said. Since UML is only a representation of a state machine , it doesn't give any hint on what you try to develop (functionally speaking). — A. Kieffer, Nov 15 '16 at 16:32
@A.Kieffer The /Entry is only executed once, when a transition occurred to its state (similar to an action). /Do is easy to implement, because the state machine is inside a process, and the code is executed until a transition occurs, is there when you can implement an /exit. But, I still don't know how to implement some code to be executed once... In a efficient way — ferdepe, Nov 15 '16 at 21:45

score 0 · Answer 1 · answered Nov 16 '16 at 09:00

0

If I understood well you just want to describe an FSM in VHDL? To do so you first need do declare all you possible states in a TYPE

TYPE my_state_type IS (s0, s1, s2);

Then you have to create a signal which takes my_state_type as a type.

SIGNAL my_state : my_state_type := s0; -- for initialisation

Then, in your process you indeed need a CASE for each of your state.

fsm : PROCESS (clk, rst)
BEGIN
    IF (rst = '1') THEN
      my_state <= s0 ;  -- reset value
    ELSIF (rising_edge(clk)) THEN
      CASE my_state IS

          WHEN s0  => output <= '1'; -- do 
                      IF (input = '1') THEN -- condition to enter s1
                         my_state <= s1; 
                      ELSE                  -- condition to stay in s0
                         my_state <= s0; 
                      END IF;

          WHEN s1  => my_state <= s2; -- stay in s1 for only one clk cycle

          WHEN s2  => my_state <= s0; -- stay in s2 for only one clk cycle

          WHEN OTHERS => my_state <= s0;

      END CASE;
    END IF;
END PROCESS;

I hope it answered your question or at least will help.

answered Nov 16 '16 at 09:00

A. Kieffer

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You don't need a `when others` clause if your state variable is an enumerated type. – scary_jeff Nov 16 '16 at 13:32
Indeed, but it became a routine for me to specify an `OTHERS` case just in case – A. Kieffer Nov 16 '16 at 14:17
Ok! You just put when to write a _do/_ in a UML state chart with `output <= '1'`, an _exit/_ can be implemented in the if statement of `s0`. But where is the _/entry_ ?? I'm looking for [that](http://www.barrgroup.com/images/articles/IntroHierarchicalStateMachines02UmlStateDiagram.gif) and not for how to implement a general FSM in VHDL. Thanks! – ferdepe Nov 17 '16 at 08:41
Your _/entry_ action can be associated with the condition `IF (input = '1') THEN `. You'll enter the new state `s1` by executing only one time the action in the condition. You can perhaps write `IF (input = '1') THEN my_state <= s1; output <= '0'; `. There you have your /entry action – A. Kieffer Nov 17 '16 at 09:04
If you want to create a global_ /entry_ action maybe you can try the condition `IF (my_state = s0 and my_state_prev /= s0 ) THEN ` in an other clocked process where **my_state_prev** takes **my_state** value after each cycle – A. Kieffer Nov 17 '16 at 09:21

/Entry in an UML state diagram with VHDL

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