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I can use += to append to recursive-expanded variable and it works well.

In real world it's sometimes required to prepend or to wrap variable into some code without expanding.

I've found similar question here GNU make: prepend a recursively expanded variable? But was unable to change it quickly for my case.

Basically I need something like this:

define Xdef
    @echo $(1)
endef

define Xdef
    @echo Before
    # Value of original Xdef is here. i.e. echo $(1)
    @echo After
endef

all:
    $(call Xdef,Hello world)

With next results:

$ make
Before
Hello world
After

Thanks.

Community
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Sergey
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  • I'm not sure what you want to do is possible. If you attempt to reference a deferred variable within its own definition, it will not expand properly (I just tried and make crashes). If you attempt to use an immediate definition, the variables are expanded right away, so `$(1)` resolves to blank. – John Nov 09 '16 at 20:24

1 Answers1

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Ok, you got me thinking about this, and it is possible -- though it's ugly, and I would strongly suggest against using this, as you'll confuse the hell out of anyone trying to maintain the makefile. You can do it by creating a new definition in the makefile. The original definition has to be a ?=, so it will not override the new definition when the makefile is reparsed...

include new.mak

define Xdef ?=
        @echo $(1)
endef

.PHONY: all

all:
        @echo running $@
        $(call Xdef,hello world)


new.mak: Makefile
        @echo rebuilding $@
        @echo "define Xdef =" >> $@
        @echo "    @echo Before" >> $@
        @echo '$(call Xdef,\$$(1))' >> $@
        @echo "    @echo After" >> $@
        @echo "endef" >> $@

clean:
        rm new.mak
John
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