How can i declare a series of signal using generate statement in VHDL? i use generate statement but i can't compile code because of errer.
architecture DATAFLOW of P_2 is
signal L3_0 : std_logic ;
signal L3_1 : std_logic ;
signal L3_2 : std_logic ;
signal L3_3 : std_logic ;
signal L3_4 : std_logic ;
signal L3_5 : std_logic ;
signal L3_6 : std_logic ;
signal L3_7 : std_logic ;
------------------------
signal L2_0 : std_logic ;
signal L2_1 : std_logic ;
signal L2_2 : std_logic ;
signal L2_3 : std_logic ;
------------------------
signal L1_0 : std_logic ;
signal L1_1 : std_logic ;
------------------------
signal L0_0 : std_logic ;
------------------------
begin
L3_0 <= DATA_IN(0) xor DATA_IN(1);
L3_1 <= DATA_IN(2) xor DATA_IN(3);
L3_2 <= DATA_IN(4) xor DATA_IN(5);
L3_3 <= DATA_IN(6) xor DATA_IN(7);
-----------------------
L2_0 <= L3_0 xor L3_1;
L2_1 <= L3_2 xor L3_3;
end DATAFLOW;
thank for your helping. I also use block statement but i can't declare signal in declaration part.
architecture DATAFLOW of P_2 is
begin
u1 : for i in 0 to 7 generate
signal L3_i : std_logic ;
begin
end generate;
u2 : for i in 0 to 3 generate
signal L2_i : std_logic ;
begin
end generate;
u3 : for i in 0 to 1 generate
signal L1_i : std_logic ;
begin
end generate;
u4 : for i in 0 to 0 generate
signal L0_i : std_logic ;
begin
end generate;
end DATAFLOW;
