A nop instruction is defined as:
sll $0,$0,0
Since $0 is a read-only register, could a nop ever be stalled in the 5-stage MIPS pipeline? That is, could it ever take more than 5 cycles to execute?
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2You didn't mention the processor. That makes the question meaningless. – Gene Oct 26 '16 at 00:30
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Just using the 5-stage MIPS pipeline. – ineedahero Oct 26 '16 at 00:39
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3Please edit the question. – Gene Oct 26 '16 at 00:40
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@ineedahero There is no such thing as a “5 stage MIPS pipeline.” Every processor has a slightly different pipeline, so specify one. – fuz Oct 26 '16 at 11:33
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1The [classic-RISC pipeline](https://en.wikipedia.org/wiki/Classic_RISC_pipeline) is a well-known thing. Clearly that's what the OP really means. – Peter Cordes Nov 02 '16 at 07:08
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I will not be stalled.
Update: Now come to think of it, may be there is a way to stall it if you really want to. If the instruction misses in the cache, the instruction fetch stage can be stalled.
Isuru H
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