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I'm getting an illegal opcode on a 64-bit Intel Xeon processor. When the exception occurs, %rip points to instruction sequence 66 66 90. According to what I've read (e.g., this article), this is a multi-byte NOP. The article seems to suggest that the preferred/mandatory byte sequences for multi-byte NOP may differ between Intel (0F 1F mod-000-rm) and AMD (66 ... 90). Can anyone tell me 1) whether either form can be used on either processor and 2) whether there are specific processor modes in which a multi-byte NOP would generate an invalid opcode exception?

BPS
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    Works fine here on Xeon E5-2620. The manual says "_it is only useful to include up to one prefix_" but doesn't specifically prohibit multiple prefixes. – Jester Oct 20 '16 at 22:59
  • Hmm... it doesn't seem to be documented as invalid, but it's not clear whether it would be interpreted as a NOP or `XCHG AX,AX`. – Ross Ridge Oct 20 '16 at 23:00
  • How exactly did you test this? Can you reproduce it if you put `db 0x66, 0x66, 0x90` (and an exit system call) into a `.asm` file and build an executable from that? I'd be shocked if there's a CPU that doesn't run that as either a NOP or a (slower but still no effect) `XCHG AX,AX`. GNU as uses `66 90` as a NOP, and a redundant prefix shouldn't affect anything. – Peter Cordes Oct 21 '16 at 03:55
  • Opcode 66h is Group 3 prefix, Intel manual 2.1.1 discourages of using more than one prefix of each group: *Other use of 66H prefix is reserved; such use may cause unpredictable behaviour.* 666790h or 0F1F00h should be OK. – vitsoft Oct 21 '16 at 07:35
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    @PeterCordes It's actually the first instruction in the linux kernel's apic_timer_interrupt handler. – BPS Oct 21 '16 at 14:35
  • @vitsoft Hmm... I see that it says, "For each instruction, it is only useful to include up to one prefix code from each of the four groups". But "useless" is not necessarily the same as "invalid" in this context. I guess the question becomes, does the "other use" susceptible to "unpredictable behavior" refer to "useless" or only "invalid" use of the 66h prefix? I've seen a good bit of unofficial documentation that seems to suggest that redundant prefixes are harmless (though they may have pipeline side-effects because of the extra time required to fetch them). – BPS Oct 21 '16 at 14:46
  • @BPS: fetch is just a code-size issue. It's decode where lots of extra prefixes are a problem for low-power CPUs like Atom and Silvermont. According to [Agner Fog's microarch pdf](http://agner.org/optimize/), Intel Silvermont takes 4 or 6 cycles to decode an instruction with more than 3 total prefixes and escape bytes (like `0F`), so SSSE3 instructions are already at the limit of 3 with no REX prefix. Other CPUs that are bad with lots of prefixes don't include escape bytes in their limit of 3. I've never seen any mention of redundant prefixes making the instruction invalid, other than >15B – Peter Cordes Oct 21 '16 at 20:17

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