64 bit LFSR output in verilog

Question

I am trying to get 64 bit output from an LFSR. I found a code in the net and edited it for 64 bit. But I am not getting the output.

    module LFSR8_8E(reset_, clock, q, lfsr_to);
    input clock, reset_;
    output [63:0] q, lfsr_to;

    reg [63:0] LFSR;
    wire  lfsr_to;
    assign lfsr_to = (LFSR == 64'h9C69832196724182);

    always @(posedge clock or negedge reset_)
    begin
    if (!reset_) LFSR[63:0] <= 64'h0000000000000000;
      else
    begin
    if (lfsr_to) LFSR[63:0] <= 64'h0000000000000000;
    else
    begin
    LFSR[63:63] <= LFSR[62:62]^LFSR[61:61]; 
    LFSR[62:62] <= LFSR[61:61]^LFSR[60:60];
    LFSR[61:61] <= LFSR[60:60]^LFSR[59:59];
    LFSR[60:60] <= LFSR[59:59]^LFSR[58:58];
    LFSR[59:59] <= LFSR[58:58];   
    LFSR[58:58] <= LFSR[57:57]; 
    LFSR[57:57] <= LFSR[56:56]; 
    LFSR[56:56] <= LFSR[55:55]; 
    LFSR[54:54] <= LFSR[53:53]; 
    LFSR[53:53] <= LFSR[52:52]; 
    LFSR[52:52] <= LFSR[51:51]; 
    LFSR[51:51] <= LFSR[50:50];
    LFSR[49:49] <= LFSR[48:48]; 
    LFSR[48:48] <= LFSR[47:47]; 
    LFSR[47:47] <= LFSR[46:46]; 
    LFSR[46:46] <= LFSR[45:45]; 
    LFSR[45:45] <= LFSR[44:44]; 
    LFSR[44:44] <= LFSR[43:43]; 
    LFSR[43:43] <= LFSR[42:42]; 
    LFSR[42:42] <= LFSR[41:41]; 
    LFSR[41:41] <= LFSR[40:40];
    LFSR[39:39] <= LFSR[38:38]; 
    LFSR[38:38] <= LFSR[37:37]; 
    LFSR[37:37] <= LFSR[36:36]; 
    LFSR[36:36] <= LFSR[35:35]; 
    LFSR[35:35] <= LFSR[34:34]; 
    LFSR[34:34] <= LFSR[33:33]; 
    LFSR[33:33] <= LFSR[32:32]; 
    LFSR[32:32] <= LFSR[31:31]; 
    LFSR[31:31] <= LFSR[30:30];
    LFSR[29:29] <= LFSR[28:28]; 
    LFSR[28:28] <= LFSR[27:27]; 
    LFSR[27:27] <= LFSR[26:26]; 
    LFSR[26:26] <= LFSR[25:25]; 
    LFSR[25:25] <= LFSR[24:24]; 
    LFSR[24:24] <= LFSR[23:23]; 
    LFSR[23:23] <= LFSR[22:22]; 
    LFSR[22:22] <= LFSR[21:21]; 
    LFSR[21:21] <= LFSR[20:20];
    LFSR[29:29] <= LFSR[28:28]; 
    LFSR[28:28] <= LFSR[27:27]; 
    LFSR[27:27] <= LFSR[26:26]; 
    LFSR[26:26] <= LFSR[25:25]; 
    LFSR[25:25] <= LFSR[24:24]; 
    LFSR[24:24] <= LFSR[23:23]; 
    LFSR[23:23] <= LFSR[22:22]; 
    LFSR[22:22] <= LFSR[21:21]; 
    LFSR[21:21] <= LFSR[20:20];
    LFSR[20:20]<= LFSR[19:19];
    LFSR[19:19] <= LFSR[18:18]; 
    LFSR[18:18] <= LFSR[17:17]; 
    LFSR[17:17] <= LFSR[16:16]; 
    LFSR[16:16] <= LFSR[15:15]; 
    LFSR[15:15] <= LFSR[14:14]; 
    LFSR[14:14] <= LFSR[13:13]; 
    LFSR[13:13] <= LFSR[12:12]; 
    LFSR[12:12] <= LFSR[11:11]; 
    LFSR[11:11] <= LFSR[10:10];
    LFSR[10:10]<= LFSR[9:9];
    LFSR[9:9] <= LFSR[8:8]; 
    LFSR[8:8] <= LFSR[7:7]; 
    LFSR[7:7] <= LFSR[6:6]; 
    LFSR[6:6] <= LFSR[5:5]; 
    LFSR[5:5] <= LFSR[4:4]; 
    LFSR[4:4] <= LFSR[3:3]; 
    LFSR[3:3] <= LFSR[2:2]; 
    LFSR[2:2] <= LFSR[1:1]; 
    LFSR[1:1] <= LFSR[0:0];
    LFSR[0:0] <= LFSR[63:63];
    end
    end
    end

    assign q = LFSR;
    endmodule

I am trying to get 64 bit output to drive a 64 input circuit in FPGA. When I synthesize the code its omitting the LFSR.

[Synth 8-3332] Sequential element (LFSR_reg[63]) is unused and will be removed from module LFSR8_8E.(63 more like this)

Any idea how to get this working.

Thanks in Advance

SIMULATION

Prashant · Answer 1 · 2016-10-21T04:43:16.170

The initialization value or the seed of an LFSR is critical for it to function correctly. In your design above, you assign the LFSR register a reset value or '0'. With a '0' initial value, at each clock edge the new value of the LFSR that would be computed through the XOR operation would also be '0'. Thus the LFSR will always have a value of '0'.

The synthesis tool parses your code and sees that none of the operations in your code result in any change in the value of the LFSR register. It therefore trims out the whole LFSR register and that is why you see the warning [Synth 8-3332]

The LFSR should never have a value of all zeros. If I modify the reset value to 64'hffff_ffff_ffff_ffff, the LFSR works correctly.

The modified code is as follows.

module LFSR8_8E(reset_, clock, q, lfsr_to);
  input clock, reset_;
  output [63:0] q;
  output lfsr_to;

  reg [63:0] LFSR;
  wire  lfsr_to;

  assign lfsr_to = (LFSR == 64'h9C69832196724182);

  always @(posedge clock or negedge reset_)
  begin
    if (!reset_) 
      LFSR[63:0] <= 64'hffff_ffff_ffff_ffff;
    else if (lfsr_to) 
      LFSR[63:0] <= 64'hffff_ffff_ffff_ffff;
    else
    begin
      LFSR[63:0] <= {(LFSR[62]^LFSR[61]),
                     (LFSR[61]^LFSR[60]),
                     (LFSR[60]^LFSR[59]),
                     (LFSR[59]^LFSR[58]),
                     LFSR[58:0],
                     LFSR[63]};
    end
  end

  assign q = LFSR;
endmodule

One other thing I would like to point out is that if the LFSR is a maximum length LFSR, then the condition

    else if (lfsr_to) 
      LFSR[63:0] <= 64'hffff_ffff_ffff_ffff;

is not necessary. The LFSR register will automatically roll over to the initial value. Looking at the code, I reckon that the LFSR polynomial will not generate the maximum length. You may want to have a look at some of the standard LFSR polynomials on Wikipedia

Check out the simulation of your design on EDA playground here https://www.edaplayground.com/x/5NpK

If you need to disable the LFSR based on an external signal, a modified code is available at https://www.edaplayground.com/x/n7Q

Thanks. In web I found that I need to tap 64,63,62,61 bit for 64 bit LFSR. Also, I am new to verilog and this stuff and have very little knowledge. I want to drive a benchmark code using this lfsr. So what I want basically to design an lfsr that gives 64 bit output. I have modified the code — Emily Blake, Oct 18 '16 at 06:56
@EmilyBlake You can use the code that I have provided, with little or no modification. If you follow the EDA playground link in the answer above, you will see the testbench that I used to test the design. — Prashant, Oct 18 '16 at 13:04
@prasant Is there any way to disable the LFSR while the reset signal is high? I need two LFSR acting together and one should be disabled after sometime — Emily Blake, Oct 18 '16 at 17:14
@EmilyBlake You will need another signal that will gate the output and gate the clock as well. I have created the modified code at https://www.edaplayground.com/x/n7Q. — Prashant, Oct 20 '16 at 00:22

64 bit LFSR output in verilog

1 Answers1