I'm using TI Keystone II device within which there's ARMv7-A architecture for ARM core.
When I try to use Large Physical Address Extension (LPAE), I use Long-descriptor translation table format. Here's the lines that I used for page table which is a U-Boot patch for over 2GB DDR3A access:
pgd_table[0] = 0x000000000000071dULL;
pgd_table[1] = 0x000000004000071dULL;
pgd_table[2] = 0x000000008000071dULL;
pgd_table[3] = 0x00000000c000071dULL;
The lines mean 1:1 mapping from VA to PA. What I am going to do is to map from 32-bit VA to 36-bit PA like below:
pgd_table[0] = 0x000000000000071dULL;
pgd_table[1] = 0x00000008C000071dULL; <= modified from 0x0 40000000 to 0x8 C0000000
pgd_table[2] = 0x000000008000071dULL;
pgd_table[3] = 0x00000000c000071dULL;`
What I found is that the VAs jumping into pgd_table[1] are mapped to 0x0 C0000000 area, not to 0x8 C0000000.
This seems to mean that while [39:30] bits of Long-descriptor translation format is 36-bit output physical address according to ARMv7 Reference Manual, [39:32] bits doens't have any effect.
What is the missing point here?
