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I have read this in a couple of places, but without fully understanding why. I understand why all instructions have to be word aligned to 4 bytes in MIPS32.

But then I read that a stack frame needs to be a multiple of 8, because the stack pointer needs to be double word aligned. Why?

I understand everything in the attached image, except the reason for adding empty space to pad the stack to a multiple of 8 bytes.

Stack Frame

EDIT: One source for where I read this was here, page 3, bullet 4. The other was Computer Organization & Design, 5th Edition, by Patterson and Hennessey, Appendix A.6, under the Procedure Call Example. However, it's pretty clear to me now I was mistaken to assume they were talking about MIPS32.

Nadim Hussami
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    From MSDN: _"MIPS ISA I and II, running in 32-bit mode, mandates that the stack pointer and frame pointer addresses align on 4-byte boundaries. MIPS ISA III and up, running in 64-bit mode, mandates that the stack pointer and frame pointer addresses align on 8-byte boundaries."_ Otherwise, if you tried to push a 64-bit value onto the stack using `sd` you'd get an alignment error. – Michael Sep 30 '16 at 08:52
  • Thanks Michael. So this is meant simply as a precaution to potentially accommodate a 64-bit stack pointer address or return address? Even if we're running in 32-bit mode? – Nadim Hussami Sep 30 '16 at 09:00
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    Are you sure the 32-bit MIPS requires 8-byte stack alignment at all? It sounds like Michael is saying the 8B requirement only applies in 64-bit mode. However, 8B alignment would make it easy to store `double`-precision floats on the stack in 32-bit mode, so some ABIs might well require 8B stack alignment. Anyway, please add a link to where you read this. – Peter Cordes Sep 30 '16 at 10:19
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    32-bits MIPS does *not* require 8-byte stack alignment by any hardware reason to my knowledge. It's just part of the convention required to be able to push a `long long` at any time. The convention IMHO is only is there to provide a seamless upgrade path to 64-bit. SGI MIPS machines BTW require the stack to be aligned to 16 bytes. – tofro Sep 30 '16 at 12:54
  • It is most likely a convention for performance, should be no hardware requirement, not sure how there could be really, the lower address bits would be ignored if it were a hardware requirement. – old_timer Oct 02 '16 at 22:29

1 Answers1

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The MIPS architecture can only access data types in memory that are evenly aligned with their size.

See MIPS Run by Dominic Sweetman says on page 320:

At the point where a subroutine is called, sp must be eight-byte-aligned, matching the alignment of the largest basic types - a long long integer, or a floating-point double. The eight-byte alignment is not required by 32-bit MIPS integer hardware, but it is essential for compatibility...

Thus, if you never try to push a double to the stack, you can very well live with 4-byte alignment on a 32-bit system. Whether your OS can, is another question, though.

markgz
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tofro
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