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Suppose I have a small vector:

wire [15:0] a;

and I assign it to a larger vector:

reg [31:0] b;

always @(posedge clk) begin
   b <= a;
end

What would be the result? Will b be assigned with zeros in its higher word, or will the high part remain unmodified? Something else?

I've tried searching for the answer in other sources, but all examples I've found had matching widths in the left an right operands of an assignment.

haggai_e
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2 Answers2

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The behaviour of Verilog in this case is well defined. With your example, because by default values are unsigned, you will get this behaviour:

  • if the left hand bit (bit 15) of a is 1'b0 or 1'b1 then a will be extended to 32 bits wide by zero-padding. ie bits 31 to 16 of b will be 1'b0.

  • if the left hand bit (bit 15) of a is 1'bx or 1'bz then a will be extended to 32 bits wide by copying that value. ie bits 31 to 16 of b will be 1'bx if bit 15 is 1'bz or 1'bz if bit 15 is 1'bx.

If a were signed, ie if a were declared like this:

wire signed [15:0] a;

then

  • the behaviour when the left hand bit is 1'bx or 1'bz would be the same as if it were unsigned - the value is just copied.

  • when the left hand bit is 1'b0 or 1'b1 that left hand bit is sign-extended, ie again the value of that left hand bit is just copied. This behaviour does not depend on whether b is signed or unsigned, only on whether a is signed or unsigned.

Matthew Taylor
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  • if any reg is signed or unsigned, does it create difference in hardware? – Prakash Darji Mar 31 '17 at 14:13
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    No, I don't think so. – Matthew Taylor Mar 31 '17 at 14:16
  • Can you point us the section of Verilog LRM that mentions this? – Balamurugan Apr 20 '20 at 07:33
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    @Balamurugan Not easily, no. Sorry. I've just had a quick look and couldn't find one particular section. So, how did I answer the above question? I teach Verilog and this is all summarised in one or two places in the course materials for our Verilog course. – Matthew Taylor Apr 20 '20 at 07:44
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    @Balamurugan By pure coincidence, I read [this question](https://stackoverflow.com/questions/61315969/constant-padding-in-verilog) next and it quotes from one section of the LRM that covers this, so I was able to find it: 5.7.1. – Matthew Taylor Apr 20 '20 at 07:47
  • @Mathew Thank you for the details. In the meanwhile, I also read through the Verilog 2005 LRM and found sections Section 5.4.1, Section 5.5.2 to closely state this. Cheers :) – Balamurugan Apr 22 '20 at 17:40
  • @Balamurugan I was actually referring to IEEE 1800-2017 - the current LRM, which also covers SystemVerilog. I'm glad the numbers match up! (BTW: you can download IEEE 1800-2017 for free from the IEEE website.) – Matthew Taylor Apr 23 '20 at 07:22
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the result will assign zeros in the higher order bits. synthesis also possible.

module larger(input [7:0]a, output [15:0] b);
    assign b = a;
endmodule

check for your self for this code.

venkat pasumarti
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