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I want to to implement a 3 bit counter in VHDL which has a circuit schematic shown in the figure.

https://i.stack.imgur.com/OoD7F.jpg

When I implement the code I got the following error messages:

--Actual associated with Formal OUT mode Signal 'Q' may not be a type conversion or function call

--Operation not cannot be associated with a formal of mode OUT.

I got these three error messages for associating the output of D flip flop and signals.

in FF1 Q => not q0

in FF2 Q => not q1

in FF3 Q => not q2

Here is the VHDL code for 3 bit counter:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity counter_3bit_alt is
    Port ( clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           Qout : out  STD_LOGIC_VECTOR (2 downto 0));
end counter_3bit_alt;

architecture Behavioral of counter_3bit_alt is

    component D_FlipFlop is
    Port ( clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end component;

signal q0, q1, q2 : std_logic;

begin

    FF1 : D_FlipFlop
        port map(
            clk => clk,
            clr => clr,
            D => q0,
            Q => not q0
        );

    FF2 : D_FlipFlop
        port map(
            clk => q0,
            clr => clr,
            D => q1,
            Q => not q1     );

    FF3 : D_FlipFlop
        port map(
            clk => q1,
            clr => clr,
            D => q2,
            Q => not q2
        );

        Qout <= q2&q1&q0;
end Behavioral;

VHDL code for D Flip Flop is

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FlipFlop is
    Port ( clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end D_FlipFlop;

architecture Behavioral of D_FlipFlop is
begin
    process(clk, clr)
        begin
            if (clr = '1') then
                q <= '0';
            elsif(rising_edge(clk)) then
                q <= D;
            end if;
    end process;

end Behavioral;
michi.b
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Umit Guden
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  • The schematic flipflop provides 2 outputs, the VHDL flipflop provides only one. The error messages are ultimately consequences of this mistake. –  Sep 17 '16 at 13:00

1 Answers1

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In D_FlipFlop port Q is an output. The output shall be assigned to a signal, not to a statement. Assign the output to a signal then invert that to be an input for port D.

Here is a suggestion

signal q0, q1, q2 : std_logic;
signal not_q0, not_q1, not_q2 : std_logic;

begin

FF1 : D_FlipFlop
    port map(
        clk => clk,
        clr => clr,
        D => not_q0,
        Q => q0
    );
not_q0 <= not q0;

FF2 : D_FlipFlop
    port map(
        clk => q0,
        clr => clr,
        D => not_q1,
        Q => q1
    );
not_q1 <= not q1;

FF3 : D_FlipFlop
    port map(
        clk => q1,
        clr => clr,
        D => not_q2,
        Q => q2
    );
not_q2 <= not q2;

Qout <= q2 & q1 & q0;
end Behavioral;
Thanushan
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