I have two Application processors that I would like to connect to using Ethernet connection. both of these AP are about 15 inches apart. Both of these processors have built in Ethernet MAC. Typical way is to add in an Externet Eth PHY IC on both sides.
Is it possible for me to ditch the Ethernet PHY totally and just connect the Eth MAC using MII interface directly?
According to microcontroller - what is the difference between PHY and MAC chip - Electrical Engineering Stack Exchange, what a PHY chip does is basically DAC/ADC:
A PHY chip or layer converts data between a "clean" clocked digital form which is only suitable for very-short-distance (i.e. inches) communication, and an analogue form which is suitable for longer range transmission. It has no particular clue as to what any of the bits "mean", nor how they should be interpreted or assembled.
So, this is theoretically possible. But, since MII is a standard specifically designed to interact with a PHY (e.g. Media-independent interface - Wikipedia mentions some registers), additional circuitry is likely to be needed.
In fact, they already explored this matter at Direct MAC-MAC connection to Ethernet switch without a PHY | NXP Community. According to it, you'll at least need a 125MHz clock signal (for Fast Ethernet).
Yes,it's possible to connect two MACs directly via RGMII connection. Only difference will be that in case of MAC-MAC connection TX of one MAC will be connected to RX of another. In case of MAC-PHY connection TX and RX signals of MAC are connected to respective TX and RX signals of PHY. .
There are variants of the MII (GMII; RMII; SGMII; RGMII...) interface for connecting MACs to PHYs or MACs to MACs, in some of them there is a MAC or PHY role.
The RGMII interface is a dual data rate (DDR) interface that consists of a transmit path and a receive path. Both paths have an independent clock, 4 data signals and a control signal. This means that in RGMII there is no PHY or MAC role, so no special support is needed for MAC-to-MAC connection as it is the case, being both ends in RGMII mode is enough for the communication to be carried out.
The RGMII standard specifies that data and clock be output simultaneously (ie. without any skew on the clock) but for proper sampling of the data signals at the receiver side, the RGMII standard specifies that skew be added to the clock signal, either by the PCB traces, or internally by any of the MACs.
Despite existing 2 independent clock paths it's necessary that both clocks run at the same frequency, for example 25Mhz for a 100Mbps link, or 125Mhz for a 1000Mbps link.
