-1

I am using UPPAAL model checker to model synchronous circuit at the gate level, I have some confusion on how I can model the clock, my goal is to verify that set-up time and hold time are not violated. I found some models giving the clock as a test vector in the appal model checker, like a t=10 for example equivalent for a rising edge and a t=20 is a falling edge , which make it looks like more like a test vector. Can anyone suggest a basic example on how to model synchronous circuit in UPAAL ?

Thank you

Hachani Ahmed
  • 19
  • 2
  • You need to be familiar with timed automata, please check the Uppaal tutorial. If you can provide a timing diagram, then it is quite straightforward to model it as a state machine with some clock guards and invariants. – mariusm Sep 09 '16 at 11:40
  • Thank you @mariusm for your answer, I had a look on the UPPAAL and not sure how the Timing diagram can help , I am actually working to model a D flip flop at the gate level, and verify the setup time and hold time, but when it come to model the clock I had a confusion how I can model it as an automata, because the best thing I found so far is giving the clock as a test vector, like , like 8 states model for example correspond to 8 rising edges, which is more likely to be a test vector, I am not sure how I can the clock space so I can verify the D Flip Flop behaviour at every rising edge. – Hachani Ahmed Sep 10 '16 at 21:12
  • I don't understand the "test vector" part. As for the synchronous clock, you need to model one process which emits on (broadcast) channels `rise` and `fall` with the given timing (modeled by guards and invariants using `clock` variable), and then other connected components would listen to those channels and update their states accordingly. – mariusm Sep 11 '16 at 14:28

1 Answers1

0

In declarations write this:

clock t;
broadcast chan rise, fall;

Then the synchronous clock in Uppaal would look like this:

Synchronous clock in Uppaal

Then other connected components should listen with rise? and fall? as synchronization on edges.

mariusm
  • 1,483
  • 1
  • 11
  • 26
  • Thank you mariusm for your explanation , the part that I do really have confusion with , is my D flip flop input, I had a model of the D flip flop behaviour, but I am not sure how to model the D flip flop input, either I model it as 2 states automata swithching between 0 and 1 every time (considering the delay ) or either I give it as a sequence like the first "0_logique" state will remain X time then the next "1_logique" state wil remain X time, especiallay I need my input to respect setup time and hold time of the clock. – Hachani Ahmed Sep 14 '16 at 08:57
  • @HachaniAhmed, you will most likely need more intermediate states. Start with two locations and then add edges for each event on inputs modeling what needs to happen. Keep adding the edges until all locations can handle any input at any time. It will probably require some waiting time in the intermediate states (model the waiting with invariants and guards) -- it's a bit tedious, but that's normal, because the actual electronics is also non-instantanious and needs some time to change the state. – mariusm Sep 14 '16 at 12:40