I need to write a Makefile to compile the next project:
project
\_ src
\_ *.c
\_ include
\_ *.h
\_ build
\_ Makefile
\_ obj
\_ output_library.so
I am new to Makefile's language and by now I have all the files in the same directory and compile with this Makefile:
SRC=../src
OUTDIR=../obj
CFLAGS=-ggdb -O1 -fPIC -Wall
LDFLAGS=-shared -ggdb -fPIC -Wall
all: libX.so
libX.so: X1.o X2.o X3.c
$(CC) -o $@ $^ $(LDFLAGS)
clean:
rm *.so *.o || true
But i get prompted:
make: *** No rule to make target 'X1.o', needed by 'libX.so'.
What's obvious as i feel i'm not making use of $SRC and $OUTDIR