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In reading the Verilog specification, I noticed a peculiar syntactical construct involving specifying path pulses. Specifically, statements in the form

PATHPULSE$in_port$out_port = ...;

According to the spec, in_port and out_port can either be identifiers (which includes \-escaped identifiers) or identifiers with a []-bracketed range.

Ignoring issues with tokenizing the PATHPULSE construct with brackets, there still seems to be a potential ambiguity issue since $ can be part of normal identifiers. For example, if a module is declared like:

module my_mod(
    input foo,
    output bar$baz,
    input foo$bar,
    output baz
);
...

Then given a path pulse statement:

PATHPULSE$foo$bar$baz = ...;

There's no way to determine which $ separates the input and output ports.

My question is this: is there a better way to tokenize PATHPULSE constructs to avoid this ambiguity? Or is this a shortfall of Verilog?

Drew McGowen
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  • Is it about the specify blocks which assigns delays to the paths? Maybe you can refer [here](https://www.hdlworks.com/hdl_corner/verilog_ref/items/Specify.htm) about `specify` block. – sharvil111 Aug 28 '16 at 11:34

1 Answers1

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This is a known shortfall of the PATHPULSE syntax. See https://accellera.mantishub.io/view.php?id=1050. It's best to avoid using $ in an identifier.

Escaped identifiers are not a problem because they are always terminated with a space.

dave_59
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