I am doing a mux 4:1 on verilog, but the output is not the expeted

Question

I've seen some examples on internet about mux 4:1 on verilog. I've tried to do something but the output is not the expeted. This is the source :

module mux41 (a, b, c, d,select,z);

input a,b,c,d;
input [1:0]select;
output reg z;

always@(select )
begin
case (select)
    2'b00: assign z=a;
    2'b01: assign z=b;
    2'b10: assign z=c;
    2'b11: assign z=d;
endcase
end
endmodule

and this is the testbench :

module mux41_tb;

reg at,bt,ct,dt;
reg [1:0] selectt;
wire zt;

mux41   test(.a(at),.b(bt),.c(ct),.d(dt),.select(selectt),
            .z(zt));
            
initial
begin
     $monitor ("a=%d",at,"b=%b",bt,"c=%b",ct,
                    "d=%b","select=%b",selectt,"z=%z",zt);
                    
    selectt =2'b00;
    #5
    selectt =2'b01;
    #5
    selectt =2'b10;
    #5
    selectt =2'b11;
    #5;
    
end

endmodule

but the output is the following :

My question is what I should chance in both codes (source and testbench).

Answer 1

You're getting

a=xb=xc=x

Because you never gave a, b, or c any values. You assign z to a for example, but a has no value since at has no value, so you're just getting x.

As for

d = 0111...

It's because of your monitor line

$monitor ("a=%d",at,"b=%b",bt,"c=%b",ct,
                "d=%b","select=%b",selectt,"z=%z",zt);

You forgot dt

$monitor ("a=%d",at,"b=%b",bt,"c=%b",ct,
                "d=%b",dt,"select=%b",selectt,"z=%z",zt);