I'm looking to use Sphinx to document VHDL source code. Ideally I'd like to be able to take a VHDL type like this:
type T_SDRAM_REQ is record
req : STD_LOGIC;
wr : STD_LOGIC;
address : STD_LOGIC_VECTOR;
wr_data : STD_LOGIC_VECTOR;
wr_ben : STD_LOGIC_VECTOR;
end record T_SDRAM_REQ;
And use a RST directive something like this:
.. vhdl:type:: sdram_pack.T_SDRAM_REQ is record
:members:
To extract all of the fields from the source code and RST-ify them for me.
I've created a Sphinx domain, but it's dawning on me that this alone is not going to be enough - that's just a bunch of custom directives really. What I actually want is something akin to autoclass or automodule, which scans Python source files to generate directives.
However as far as I can tell the Sphinx automodule functionality is just for Python. Is it possible to extend Sphinx to include similar functionality for other languages? In VHDL that would probably be called autopackage or autoentity, in C++ I guess autonamespace or a different autoclass? Could I somehow add a vhdl:autopackage::
directive to my domain? From what I can tell from the Sphinx source I don't think the automodule directive is part of the Python domain.