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I have extracted how many flops (floating point operations) each of my algorithms are consuming,

  • I wonder if I implement this algorithms on FPGA or on a CPU, can predict (roughly at least) how much power is going to be consumed?

Both power estimation in either CPU or ASIC/FPGA are good for me. I am seeking something like a formula. I have this journal paper, for Intel CPUs. It gives power consumption per instruction (not only floating point operation but all those addressing, control, etc. instructions) so I need something more general to give power based on FLOPS not number of instructions of the code in a special processor.

Paul Floyd
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Mehdi
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  • I'v found a paper in this "https://www.top500.org/files/green500/balaji-power-meas-green500-greencom10.pdf", it is for some particular processor. – Mehdi Aug 11 '16 at 16:19
  • It's strongly dependent on the exact outcome of routing, and the FPGA architecture. What's wrong with using your FPGA toolkit's power estimator tool (based on good post-PAR simulation data)? – nanofarad Aug 11 '16 at 17:23
  • Its HDL coding FPGA implementation takes a huge time of me, whereas it is just a small portion of my work. – Mehdi Aug 13 '16 at 12:54
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    If you can't create a circuit design using HLS or HDL or whatever, then estimating the power consumption of the circuit is moot. – nanofarad Aug 13 '16 at 16:58
  • I know, but in my case it can be justified. I want it as rule of thumb, You know my algorithm has 1000 flops whereas its counterpart has 10^6 or more flops, the difference is obvious, but for completion of my argument I need to mention something related to power. – Mehdi Aug 13 '16 at 17:01
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    As I said again, it really depends on the exact routing outcome and process technology (although rules of thumb exist, they are not always valid). The power consumption would correlate with the number of logic elements, as well as the switching frequency on signals (since CMOS logic is otherwise static and characterized mainly by transistor leakage) – nanofarad Aug 13 '16 at 17:47
  • @hexafraction, You a right. I'v found a metric named FLOPS/watts, this is great for my problem, however I cann't find anything that is generalize it. Like what is FLOSP/Watts of Pentuim 3 , what is FLOSP/Watts TI DSP, or ARM Cortex11, etc. – Mehdi Aug 13 '16 at 18:17

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Re CPU: It's not really possible with modern architectures. Let's assuming your program is running on bare metal (i.e. avoiding the complexities of modern OSs, other applications, interrupt processing, optimizing compilers, etc). Circuitry that isn't being used, the modern processor will operate at a reduced power level. There are also hardware power conservation states such as P (Power) and C (Sleep) states that are instruction independent and will vary your power consumption even with the same instruction sequence. Even if we assume your app is CPU-bound (meaning there are no periods long enough to allow the processor to drop into hardware power saving states), we can't predict power usage except at a gross statistical level. Instruction streams are pipelined, taken out-of-order, fused, etc. And this doesn't even include the memory hierarchy, etc.

FPGA: Oh, heck. My experience with FPGA is so old, that I really don't want to say from when. All I can say is that way back, when huge monsters roamed the earth, you could estimate power usage since you knew the circuit design, and the power consumption of on and off gates. I can't imagine that there aren't modern power conservation technologies built into modern FPGAs. Even so, what small literature I scanned implies that a lot of FPGA power technology is based upon a-priori analysis and optimization. See Design techniques for FPGA power optimization, and 40-nm FPGA Power Management and Advantages. (I just did a quick search and scan of the papers, by the way, so don't pay too much attention to my conclusion.)

Taylor Kidd
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