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I'm kinda confused about the exact definition of a "machine cycle".

For example, some source online say that it is:

The four steps which the CPU carries out for each machine language instruction: fetch, decode, execute, and store.

While the book Programming the Z80, which supposedly has a good reputation, says:

We have seen that all instructions are executed in three phases: FETCH, DECODE, EXECUTE. We now need to introduce some definitions. Each of these phases will require several clock cycles. The Z80 executes each phase in one or more logical cycles, called a "machine cycle."

Now what confuses me here is that - from what I understood - the first one is basically saying: A machine cycle is a fetch-decode-execute cycle, while the book is basically saying: A machine cycle is the one - or more - clock cycle that happens in each fetch, decode or execute cycle individually.

So, what is what?

Abdelrahman Eid
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  • https://en.wikipedia.org/wiki/Instruction_cycle – YOU Aug 06 '16 at 16:23
  • @YOU Yes, I read that, and that is what I'm showing in the first example. Now does that mean that the book's definition is incorrect? – Abdelrahman Eid Aug 06 '16 at 16:26
  • the first says "steps". it clearly doesn't name the concept. – Karoly Horvath Aug 06 '16 at 16:29
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    anyways, in modern processors these steps overlap... – Karoly Horvath Aug 06 '16 at 16:29
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    I would not get too wrapped up in definitions. There's _lots_ of inconsistency in terminology in the discipline because it has roots in several others and it changes so fast. Different authors generally choose one and then clarify by explaining what they mean. That's what you're seeing here. In other less dynamic subjects, terminology is more consistent. IME, "cycle" can mean either the execution of one instruction or a tick of the machine clock. Modern processors have very complex datapaths and multi-phase clocks, so neither term is precise. – Gene Aug 06 '16 at 17:27

2 Answers2

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z80 has two different concepts of "cycle". The distinction matters, because z80 is a multi-cycle architecture, and it uses both multiple clock cycles per "step" and (often) multiple "steps" per instruction.

The "steps" are called machine cycles (M-cycles), they do "high level" tasks such as reading from memory, doing an ALU operation, etc. Complex instructions such as inc (iy+42) take many machine cycles, for decoding the prefix, the main opcode, reading the offset, adding it to iy, doing the increment, and writing back the result. Conditional jumps even have a varying number of M-cycles, they omit the M-cycle that does that actual jumping if the condition is false.

Each M-cycle then takes multiple (3 to 6) clock cycles (aka T-cycle or T-state, this terminology has mostly died unless referring to old multicycle processors). For example, a memory read will take 3 cycles, an opcode decode typically takes 4, some internal operations take 5, and 16bit increments seem to extend the OCF by an other 2 cycles somehow.

That's all quite z80-specific.

Elsewhere the term "machine cycle" has been used to refer some sort of "complete trip" of an instruction from start to finish. That's not what would be meant in a z80 context.

harold
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  • Pedantic: conditional `JP` costs the same regardless of whether the branch is taken; `JR`, `CALL` and `RET` have variable timing though, hence why I'm classifying this comment as perhaps not so necessary. `CALL`'s an interesting one though: per the documentation it decides whether it'll make the call before it has finished reading the operand and throws an extra wait state into the third byte fetch only if it needs to adjust the SP. So it loads the extra work into the existing machine cycle (though, probably, that's implented as picking a different machine cycle). – Tommy Jun 20 '17 at 17:46
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The four steps which the CPU carries out for each machine language instruction: fetch, decode, execute, and store.

Each of these steps would typically happen in a different cycle. "Execute" is a complicated process involving some sub-steps and plenty of transistors, but for most instructions it can still be done in a single cycle. That's part of the reason for putting the boundaries between parts of the CPU in those places.

the first one is basically saying: A machine cycle is a fetch-decode-execute cycle

No, it isn't saying that. That's completely wrong. Old non-pipelined CPUs usually have a throughput of less than one instruction per cycle, because each instruction takes multiple cycles before the next one can start.

A CPU clock cycle, or machine cycle, is a cycle of low voltage to high voltage and back. https://en.wikipedia.org/wiki/Clock_signal. The CPU uses this clock input to synchronize the various steps.

The max clock speed for a CPU is limited by the slowest thing that needs to happen in a single clock cycle. e.g. maybe the decode stage has a lot of gate delays, so if the clock ran any faster the result wouldn't be latched into the latch between that stage and the next stage when the clock transitioned from high to low.

A pipelined CPU will try to keep its various stages occupied at the same time, instead of waiting until one instruction is finished executing before decoding (or maybe even fetching) the next one. See https://en.wikipedia.org/wiki/Classic_RISC_pipeline

Peter Cordes
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  • Thanks for this easy explanation. But I think that this is the pure/abstract definition of a machine cycle, right? If so then which of the two examples I've provided is correct? Because from what I understood they both work in the same fundamental way, which you've just explained. – Abdelrahman Eid Aug 06 '16 at 16:56
  • @Abd-ElrhmanEid: Updated to answer the specific question. I was mostly answering the title the first time. – Peter Cordes Aug 06 '16 at 17:11