1

I'm using Icarus iVerilog to synthesize and test my code but I'm getting unknown values when logically 1's should be appearing. Here's an example of what I'm trying to do.

reg [8:0] a = 000110100;
wire [8:0] b = 0;

generate
    genvar i;
    for (i = 8; i > -1; i = i - 1)
    begin:loop
        assign b[i] = |a[8:i];
    end
endgenerate

This should produce some gates in the form of

b[8] = a[8];
b[7] = a[8] | a[7];
b[6] = a[8] | a[7] | a[6];
b[5] = a[8] | a[7] | a[6] | a[5];
...

My expected output is

000111111

I'm actually getting 

000xxxxxx

I can't find any reason for the x's, and am starting to suspect it's an issue with iVerilog.

adragon202
  • 23
  • 5
  • Does your synthesis tool support variable declaration initializations? – dave_59 Jul 31 '16 at 22:09
  • I could try this in a different tool tomorrow, but two things you could try for now: 1) use `i>=0` instead of `i>-1`, and 2) count forward from 0 instead of backward from 8. – teadotjay Aug 01 '16 at 00:17

1 Answers1

5

Please remove assignment in the declaration below. The assign wire to 0 in the declaration makes conflict with assignment 1 in genvar block

 wire [8:0] b = 0;

change to 

wire [8:0] b;

This is because

wire [8:0] b = 0;

is not an initialisation, it is a continuous assignment. It is equivalent to 

wire [8:0] b;
assign b = 0;

Hence, the conflict.

Matthew Taylor
  • 13,365
  • 3
  • 17
  • 44
babyworm
  • 89
  • 3