Please, clarify the concept of sequential and concurrent execution in VHDL

Question

I got familiar with a little bit of Verilog at school and now, one year later, I bought a Basys 3 FPGA board. My goal is to learn VHDL.

I have been reading a free book called "Free Range VHDL" which assists greatly in understanding the VHDL language. I have also searched through github repos containing VHDL code for reference.

My biggest concern is the difference between sequential and concurrent execution. I understand the meaning of these two words but I still cannot imagine why we can use "process" for combinational logic (i.e. seven segment decoder). I have implemented my seven segment decoder as conditional assignment of concurrent statements. What would be the difference if I implemented the decoder using process and a switch statement? I do not understand the word sequential execution of process when it comes to combinational logic. I would understand it if it was a sequential machine-a state machine.

Can somebody please explain this concept?

Here is my code for a seven-segment decoder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hex_display_decoder is
    Port ( D: in STD_LOGIC_VECTOR (3 downto 0);
       SEG_OUT : out STD_LOGIC_VECTOR (6 downto 0));
end hex_display_decoder;

architecture dataflow of hex_display_decoder is
begin
  with D select
      SEG_OUT <=  "1000000" when "0000",
                  "1111001" when "0001",
                  "0100100" when "0010",
                  "0110000" when "0011",
                  "0011001" when "0100",
                  "0010010" when "0101",
                  "0000010" when "0110",
                  "1111000" when "0111",
                  "0000000" when "1000",
                  "0010000" when "1001",
                  "0001000" when "1010",
                  "0000011" when "1011",
                  "1000110" when "1100",
                  "0100001" when "1101",
                  "0000110" when "1110",
                  "0001110" when "1111",
                  "1111111" when others;
end dataflow;

Thank you.

See IEEE Std 1076-2008 11.6 Concurrent signal assignment statements "A concurrent signal assignment statement represents an equivalent process statement that assigns values to signals." Other concurrent statement sections will describe how they are elaborated for simulation/synthesis. All elaborated models simulate by execution of sequential statements. How requires understanding VHDL's simulation cycle. *Free Range VHDL* may not be a sufficient resource. Should you claim your shown code is function consider the [Code Review](https://codereview.stackexchange.com/questions/tagged/vhdl) site. — , Jul 07 '16 at 01:17
This may be on-topic for Code Review, assuming **A)** the code works **and B)** the code isn't hypothetical or incomplete in any way — Quill, Jul 07 '16 at 01:35

Philippe Aubertin · Accepted Answer · 2018-09-22T15:15:27.660

My biggest concern is difference between sequential and concurrent execution. I understand the meaning of these two words but I still cannot imagine why we can use "process" for combinational logic (ex. seven segment decoder).

You are confounding two things:

The type of logic, which can be sequential or combinational.
The order of execution of statements, which can be sequential or concurrent.

Types of logic

In logic design:

A combinational circuit is one that implements a pure logic function without any state. There is no need for a clock in a combinational circuit.
A sequential circuit is one that changes every clock cycle and that remembers its state (using flip-flops) between clock cycles.

The following VHDL process is combinational:

process(x, y) begin
    z <= x or y;
end process;

We know it is combinational because:

It does not have a clock.
All its inputs are in its sensitivity list (the parenthesis after the process keyword). That means a change to any one of these inputs will cause the process to be re-evaluated.

The following VHDL process is sequential:

process(clk) begin
    if rising_edge(clk) then
        if rst = '1' then
            z <= '0';
        else
            z <= z xor y;
        end if;
    end if;
end process;

We know it is sequential because:

It is only sensitive to changes on its clock (clk).
Its output only changes value on a rising edge of the clock.
The output value of z depends on its previous value (z is on both sides of the assignment).

Model of Execution

To make a long story short, processes are executed as follow in VHDL:

Statements within a process are executed sequentially (i.e. one after the other in order).
Processes run concurrently relative to one another.

Processes in Disguise

So-called concurrent statements, essentially all statements outside a process, are actually processes in disguise. For example, this concurrent signal assignment (i.e. an assignment to a signal outside a process):

z <= x or y;

Is equivalent to this process:

process(x, y) begin
    z <= x or y;
end process;

That is, it is equivalent to the same assignment within a process that has all of its inputs in the sensitivity list. And by equivalent, I mean the VHDL standard (IEEE 1076) actually defines the behaviour of concurrent signal assignments by their equivalent process.

What that means is that, even though you didn't know it, this statement of yours in hex_display_decoder:

SEG_OUT <=  "1000000" when "0000",
            "1111001" when "0001",
            "0100100" when "0010",
            "0110000" when "0011",
            "0011001" when "0100",
            "0010010" when "0101",
            "0000010" when "0110",
            "1111000" when "0111",
            "0000000" when "1000",
            "0010000" when "1001",
            "0001000" when "1010",
            "0000011" when "1011",
            "1000110" when "1100",
            "0100001" when "1101",
            "0000110" when "1110",
            "0001110" when "1111",
            "1111111" when others;

is already a process.

Which, in turn, means

What would be the difference if I implemented the decoder using process and a switch statement?

None at all.

Please, clarify the concept of sequential and concurrent execution in VHDL

1 Answers1

Types of logic

Model of Execution

Processes in Disguise