How do I display the pulse width of a signal in vhdl?

Question

I am trying to implement this code into a program that displays the pulse width of a signal onto the seven segment display on the basys2 board but when I download the code onto the board it just displays "0001" I figured out its just showing 1 from the part that does "x<=a_count_pw+1". It looks like it just adds 1 and thats it even when there is no signal being input. I also get this warning "The signal is incomplete. The signal does not drive any load pins in the design." This is supposed to be for my input signal? Here is my code. Any help is greatly appreciated thank you.

Top module: main_top - Behaviral(main_top.vhd)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity main_top is
port(
        J3_IO1 : in std_logic;
        mclk : in STD_LOGIC;
        btn : in STD_LOGIC_VECTOR(3 downto 0);
        a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
        an : out STD_LOGIC_VECTOR(3 downto 0);
        dp : out STD_LOGIC
     );
end main_top;

architecture Behaviral of main_top is
signal a_count_rst: STD_LOGIC;
signal a_count_pw: STD_LOGIC_VECTOR(15 downto 0);
signal a_count_pw_reported: STD_LOGIC_VECTOR(15 downto 0);
signal J3_IO1_q : STD_LOGIC;
signal J3_IO1_qq : STD_LOGIC;

component main
port(
    x : in STD_LOGIC_VECTOR(15 downto 0);
    clk : in STD_LOGIC;
    clr : in STD_LOGIC;
    a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
    an : out STD_LOGIC_VECTOR (3 downto 0);
    dp : out STD_LOGIC 
);
end component;


signal x: STD_LOGIC_VECTOR (15 downto 0);
begin

process(mclk)
 if mclk'event and mclk='1' then 
-- Synchronous process, clock edge is outer "if"
  if a_count_rst='1' then --synchronous reset
   a_count_pw <= b"0000000000000000";
   a_count_pw_reported <= a_count_pw_reported; 

  else
   J3_IO1_q <= J3_IO1;  -- First D FF stage 
   J3_IO1_qq <= J3_IO1_q; -- Second D FF stage for edge detect
  if  J3_IO1_qq = '0' and J3_IO1_q = '1' then -- Detect rising edge
      a_count_pw <= b"0000000000000000"; -- Start from 0 at rising edge
  elsif J3_IO1_qq = '1' and J3_IO1_q = '0' then -- Detect falling edge
     a_count_pw_reported <= a_count_pw;  -- Capture count
   else
     x <= a_count_pw + 1;
   end if;
  end if;
 end if;
end process;


X1 : main port map
        (x=>x, clk=>mclk, clr=>btn(3), a_to_g=>a_to_g, an=>an, dp=>dp);


end Behaviral;

This is the next module for multiplexing the display.

Module: X1 - main - Behaviral (main.vhd)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity main is
    port(
    x : in STD_LOGIC_VECTOR(15 downto 0);
    clk : in STD_LOGIC;
    clr : in STD_LOGIC;
    a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
    an : out STD_LOGIC_VECTOR (3 downto 0);
    dp : out STD_LOGIC;
    btn : in STD_LOGIC_VECTOR(3 downto 0);
    J3_IO1 : in STD_LOGIC;
    a_count_pw : in STD_LOGIC_VECTOR(15 downto 0)
);
end main;

architecture Behaviral of main is
signal s : STD_LOGIC_VECTOR (1 downto 0);
signal aen : STD_LOGIC_VECTOR (3 downto 0);
signal clkdiv : STD_LOGIC_VECTOR (20 downto 0);
signal digit : STD_LOGIC_VECTOR (3 downto 0);



begin
s <= clkdiv(18 downto 17);
aen <= "1111";
dp <= '1';


--4 to 1 multiplex
process(s, x)
begin
    case s is
    when "00" => digit <= x(3 downto 0);
    when "01" => digit <= x(7 downto 4);
    when "10" => digit <= x(11 downto 8);
    when others => digit <= x(15 downto 12);
    end case;
end process;


process(digit)
begin
    case digit is
        when X"0" => a_to_g <= "1000000"; --0
        when X"1" => a_to_g <= "1111001"; --1
        when X"2" => a_to_g <= "0100100"; --2
        when X"3" => a_to_g <= "0110000"; --3
        when X"4" => a_to_g <= "0011001"; --4
        when X"5" => a_to_g <= "0010010"; --5
        when X"6" => a_to_g <= "0000010"; --6
        when X"7" => a_to_g <= "1011000"; --7
        when X"8" => a_to_g <= "0000000"; --8
        when X"9" => a_to_g <= "0010000"; --9
        when X"A" => a_to_g <= "0001000"; --A
        when X"B" => a_to_g <= "0000011"; --b
        when X"C" => a_to_g <= "1000110"; --C
        when X"D" => a_to_g <= "0100001"; --d
        when X"E" => a_to_g <= "0000110"; --E
        when others => a_to_g <= "0001110"; --F
    end case;
end process;

--digit control
process(s, aen)
begin
    an <= "1111";
    if aen(conv_integer(s)) = '1' then
        an(conv_integer(s)) <= '0';
    end if;
end process;

--clock divider
process(clk, clr)
begin
    if clr ='1' then
        clkdiv <= (others => '0');
    elsif clk'event and clk = '1' then
        clkdiv <= clkdiv +1;
    end if;
end process;

end Behaviral;

Here is my ucf file ports.ucf

NET "mclk" LOC = "B8";

NET "a_to_g<0>" LOC = "L14";
NET "a_to_g<1>" LOC = "H12";
NET "a_to_g<2>" LOC = "N14";
NET "a_to_g<3>" LOC = "N11";
NET "a_to_g<4>" LOC = "P12";
NET "a_to_g<5>" LOC = "L13";
NET "a_to_g<6>" LOC = "M12";
NET "dp" LOC = "N13";

NET "an<3>" LOC = "K14";
NET "an<2>" LOC = "M13";
NET "an<1>" LOC = "J12";
NET "an<0>" LOC = "F12";

NET "btn<3>" LOC = "A7";


NET "J3_IO1" LOC = "J3";

Your main_top process sensitive to mclk is missing a `begin`. Which signal is incomplete? It sounds like main is not bound. Consider simulating your design before proceeding to synthesis. — , Jun 21 '16 at 02:10

score 0 · Answer 1 · answered Jun 22 '16 at 06:47

As it looks to me, you haven't binded some port elements. I don't see x which you use as indicator for signal width. That also makes perfect sense if you look at the error - "The signal does not drive any load pins in the design". Elements from port should all be binded to actual pins. You could consider x as a 16 bits wide parallel interface where you read input values and later use them for your cause. As it looks to me, you could just use x as a signal or even variable and send back just actual bytes that you should write to seven segment display

How do I display the pulse width of a signal in vhdl?

1 Answers1