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My SSE-FPU generates the following NaNs:

  • When I do a any basic dual operation like ADDSD, SUBSD, MULSD or DIVSD and one of both operands is a NaN, the result has the sign of the NaN-operand and the lower 51 bits of the mantissa of the result is loaded with the lower 51 bits of the mantissa of the NaN-operand.
  • When both operations are NaN, the result is loaded with the sign of the destination-register and the lower 51 bits of the result-mantissa is loaded with the lower 51 bits of the destination-register before the operation. So the associative law doesn't count when doing multiplications on two NaN-operands!
  • When I do a SQRTSD on a NaN-value, the result has the sign of the NaN-operand and the lower 51 bits of the result is loaded with the lower 51 bits of the operand.
  • When I do a multiplication of infinity with zero or infinity, I always get -NaN as a result (binary representation 0xFFF8000000000000u).
  • If any operand is a signalling NaN, the result becomes a quiet NaN if the exception isn't masked.

Is this behaviour determined anywhere in the IEEE-754-standard?

Peter Cordes
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Bonita Montero
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  • *the result becomes a quiet NaN if the exception isn't masked*. I think you mean "if the exception is masked*. You don't get a result from instructions that trigger SSE math exceptions. I think at least some of this is documented in [Intel's ISA manuals](https://www-ssl.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html), but interesting question about how much of it is required or suggested by IEEE-754. – Peter Cordes Jun 18 '16 at 10:56
  • Also: I think you mean commutative, to describe the fact that normally the result of mul or add doesn't depend on which operand was the destination. (FP math isn't associative even without NaNs; `a+b+c might not equal `c+b+a` because of rounding differently) – Peter Cordes Jun 18 '16 at 11:01

1 Answers1

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NaN have a sign and a payload, together are called the information contained in the NaN.
The whole point of NaNs is that they are "sticky" (maybe Monadic is a better term?), once we have a NaN in an expression the whole expression evaluate to NaN.
Also NaNs are treated specially when evaluating predicates (like binary relations), for example if a is NaN, then it is not equal to itself.

Point 1
From the IEEE 754:

Propagation of the diagnostic information requires that information contained in the NaNs be preserved through arithmetic operations and floating-point format conversions.

Point 2
From the IEEE 754:

Every operation involving one or two input NaNs, none of them signaling, shall signal no exception but, if a floating-point result is to be delivered, shall deliver as its result a quiet NaN, which should be one of the input NaNs.

No floating point operation has ever been associative.
I think you were looking for the term commutative though since associativity requires at least three operands involved.

Point 3
See point 4

Point 4
From IEEE 754:

The invalid operations are
1. Any operation on a signaling NaN (6.2)
2. Addition or subtraction – magnitude subtraction of infinities such as, (+INFINITY) + (–INFINITY)
3. Multiplication – 0 × INFINITY
4. Division – 0/0 or INFINITY/INFINITY
5. Remainder – x REM y, where y is zero or x is infinite
6. Square root if the operand is less than zero
7. Conversion of a binary floating-point number to an integer or decimal format when overflow, infinity, or NaN precludes a faithful representation in that format and this cannot otherwise be signaled
8. Comparison by way of predicates involving < or >, without ?, when the operands are unordered (5.7, Table 4)

Point 5
From IEEE 754:

Every operation involving a signaling NaN or invalid operation (7.1) shall, if no trap occurs and if a floating-point result is to be delivered, deliver a quiet NaN as its result.

Due to its relevance, the IEEE 754 standard can be found here.

Margaret Bloom
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  • I found the IEEE-754-2008 specification here: http://www.csee.umbc.edu/~tsimo1/CMSC455/IEEE-754-2008.pdf - it seems to be more precise. – Bonita Montero Jun 18 '16 at 12:09
  • @BonitaMontero Thanks Bonita, I can't access that server though: 403. – Margaret Bloom Jun 18 '16 at 12:11
  • I found an interesting thing: When I do a operation on two operands with the x87-FPU and both are NaN, the mantissa of the resulting quiet NaN is the larger value of 51 bit of both operands. What drugs were they smoking at Intel? – Bonita Montero Jun 18 '16 at 13:37
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    @BonitaMontero When both operands are NaN the implementation is free to chose one of their payload as the result's payload. I don't know what you have observed is an meaningful decision or just a convenient one (to reuse transistors). – Margaret Bloom Jun 18 '16 at 14:40
  • That's what can also be found in the IEEE-spec. But this behaviour unfortunately isn't continued with SSE. – Bonita Montero Jun 18 '16 at 15:30
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    For completeness I will point out that while IEEE-754 recommends ("should") that operations involving a NaN source operand return the NaN source operand (or either one of two NaN source operands), possibly converted to QNaN as needed, this is not mandatory ("shall"). In particular, returning a single canonical NaN pattern in such cases is compliant with the standard. So propagation of NaN "payloads", while sometimes useful, is not mandated or guaranteed by the standard. – njuffa Jun 19 '16 at 05:39