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Many parts in kernel memory are non-page-able.

  1. What is the setting of page tables for these areas and how logical to physical mapping is done for them?

  2. Is there any relation between identity mapping and the wired memory (non-page-able memory)?

ultimate cause
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1 Answers1

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For non-paged memory, all the system has to do is ensure that a physical page frame is mapped to the logical address and that the page frame is not unmapped. The page tables are usually the same for paged and nonpaged memory.

user3344003
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  • Thanks. Isn't it true that, if the memory is non-pageable we do not really big address translation effort, because, an address we look for, will always be there at a certain offset from certain base point primary memory? Why do we still need page tables populated for them? – ultimate cause Jun 13 '16 at 04:18
  • You need a page table on most systems so that the kernel code can access the memory. Even kernel code uses logical address translation. – user3344003 Jun 13 '16 at 17:06
  • Yes. I agree on that. Paged or Non-Paged every address is a virtual address. What I actually meant is, in case some thing has to be permanently stationery in RAM, then why do we waste PTE for them. We could just have a special registers that hold starting virtual/physical address pair of each of these locations and rest of the translation will be an arithmetic operation. Since this area will never fault, we can use PTEs entries for something different. Thanks for your reply though. – ultimate cause Jun 13 '16 at 18:39
  • Then how to have those locations in non-fixed locations in memory and how does the processor treat those locations the same as any other location? – user3344003 Jun 14 '16 at 16:03
  • MMU could be slightly modified so that a working set of non-paged memory enjoys the translation by adding(or subtracting) a constant base value after being loaded. As I understand, processor never had any say in how the address is accessed. Only if MMU raised a page-fault exception (for paged memory), an interrupt handler will trigger demand paging sequence. Locations do not matter, because, addresses will be formed only after a module is loaded. Therefore, programming of "modified" MMU will be done only after this loading happens, in absolutely same way as TLB is loaded for dynamic memory. – ultimate cause Jun 14 '16 at 19:21