I've been trying to get this code that I whipped up on a whim. For the most part, I think I'm sure the modules themselves are okay. Its the test bench that's throwing up all the errors.
Here's the code in its entirety:
/*
Primitive code to control a stepper motor using FPGA
It will run as a seconds hand
9 June 2016
dwiref024
*/
module clock_divider(clock, reset, clock_div);
input clock;
input reset;
output clock_div;
reg [25:0]counter = 26'd0;
// Assuming a clock frequency of 40Mhz
// log2(40M) = 25.25
// Therefore 40MHz corresponds to MOD25
always@(posedge clock, negedge reset) begin
if(!reset) begin
counter <= 26'd0;
end
if(counter == 26'd40000000) begin
counter <= 26'd0;
end
else begin
counter <= counter + 1;
end
end
assign clock_div = counter[24]; // Gives you a clock signal 'clock_div'of approximate frequency 1Hz
initial begin
$dumpvars(0, clock, reset, counter);
end
endmodule
module count_seconds (
input clock_div, reset
);
reg [5:0]seconds = 6'd0;
always@(posedge clock_div, negedge reset) begin
if (!reset) begin
seconds <= 0;
end
else if (seconds == 6'd60) begin
seconds <= 0;
end
else begin
seconds <= seconds + 1;
end
end
initial begin
$dumpvars (0, clock_div, seconds);
end
endmodule
module get_servo(
input clock_div,
output reg servoPin = 0,
output reg ding
);
always@(posedge clock_div) begin
if(clock_div)
ding <= 1;
else
ding <= 0;
end
always@(ding) begin
if (ding) begin
servoPin = 1'b1;
end
else servoPin = 1'b0;
end
initial begin
$dumpvars (0, servoPin);
end
endmodule
module clk_tb;
reg clock;
reg reset;
reg servoPin;
reg clock_div;
reg ding;
initial begin
clock = 0;
reset = 0;
repeat(2) #10 clock = ~clock;
reset = 1;
forever #10 clock = ~clock;
end
clock_divider DUT1 (clock, reset, clock_div);
get_servo DUT2 (clock_div, servoPin, ding);
initial begin
servoPin = 1'b1;
#1 clock_div = 1'b0;
$finish;
end
endmodule
Upon running
$ icarusverilog -o servo servo.v
I get the following errors:
servo.v:105: error: reg clock_div; cannot be driven by primitives or continuous assignment.
servo.v:105: error: Output port expression must support continuous assignment.
servo.v:105: : Port 3 (clock_div) of clock_divider is connected to clock_div
servo.v:106: error: reg servoPin; cannot be driven by primitives or continuous assignment.
servo.v:106: error: Output port expression must support continuous assignment.
servo.v:106: : Port 2 (servoPin) of get_servo is connected to servoPin
servo.v:106: error: reg ding; cannot be driven by primitives or continuous assignment.
servo.v:106: error: Output port expression must support continuous assignment.
servo.v:106: : Port 3 (ding) of get_servo is connected to ding
6 error(s) during elaboration.
I looked across the boards here and saw questions that specified when and where you use reg in the test bench modules to avoid the this:
<variable name> is not a valid l-value in foo
That was among the first errors that I got. In trying to avoid it, I have ended up with these. If anyone could point out the root cause of these errors and where they originate from, I might be able to fix this and learn something new in the process.
