VHDL: up/down counter with two buttons

Question

I am trying to make a four bit up/down modulo10 counter. Button1 - counts up, Button2 - counts down. I'm trying to do it using rising_edge command but for two signals I can’t define with button was pressed. So in next version of program I want detect button using if statement.

library IEEE;
use IEEE.std_logic_1164.all, IEEE.numeric_std.all;

ENTITY counter is
generic (n:natural :=4);
port(
button1:        in std_logic;
button2:        in std_logic;
clear:  in std_logic;
C                               : out std_logic;
OUT1                            : out std_logic_vector(n-1 downto 0)
);
END counter;

ARCHITECTURE beh of counter is
begin

p0:process (button1, clear) is
variable count: unsigned (n-1 downto 0);
begin
        if clear = '1' then
        count:= (others=>'0');
                elsif button1='1' then
                count:=count+1;
                        elsif count=10 then
                                count:=(others=>'0');
                                C<='1';
                                else C<='0';
                        end if;

            if button2='1' then
                  count:=count-1;
                  if count=0 then
                        count:=(others=>'1');
                        C<='1';
                        else C<='0';
                  end if;
                  end if;
        OUT1<=std_logic_vector(count);
end process p0;
end architecture beh;

In Quartus program is compiled without errors, but in simulation does not work. I would be very greatfull for help. :)

Are intending to program and FPGA with this? If so, then you are a long way from where you need to be. — Matthew Taylor, May 21 '16 at 20:32
I don't have FPGA development kit, so although I would like to run simulations for now. I added button2 to sensitivity list but simulation still doesn't work. — bastik, May 22 '16 at 09:13
You would never be able to program an FPGA with this code. A counter is a _sequential circuit_ : any HW counter needs a clock. So, what you have is some arbitary "program" in VHDL, which you may or may not be able to get working. But VHDL is a _HW description language_, not a SW programming language, so I gues you're aiming for HW at some point. So, I suggest you google "vhdl counter" to see how it's done, and also take a look at my answer [here](http://stackoverflow.com/questions/36539962/errorxst827-signal-count-cannot-be-synthesized-bad-synchronous-description/36543625#36543625). — Matthew Taylor, May 22 '16 at 11:36
Here's how I've implemented it: http://electronics.stackexchange.com/a/272248/38353 — Dmitri Nesteruk, Nov 29 '16 at 21:53

score 0 · Answer 1 · answered Jun 08 '16 at 23:11

You should use a CLOCK signal to use rising_edge, I created a clock signal in your entity:

clock : in std_ulogic;

After this you should put in your process sensitivy the CLOCK signal and the button2 signal, like this:

p0:process (button1, button2, clear, clock) is

My simulation with this conditions work correctly, when I press button1 the count goes up, when I press button2 count goes down.

The complete architecture:

ARCHITECTURE beh of counter is
begin

p0:process (button1, button2, clear, clock) is
variable count: unsigned (n-1 downto 0);
begin
        if rising_edge(clock) then
            if clear = '1' then
                count:= (others=>'0');
            end if;
            if (button1='1') then
                count:=count+1;
            elsif (count=10) then
                count:=(others=>'0');
                C<='1';
            else 
                C<='0';
            end if;

            if (button2='1') then
                  count:=count-1;
            if count=0 then
                  count:=(others=>'1');
                  C<='1';
            else 
            C<='0';
            end if;
            end if;
         end if;
        OUT1<=std_logic_vector(count);
end process p0;
end architecture beh;

VHDL: up/down counter with two buttons

1 Answers1