gaussian noise in systemVerilog

Question

I'm writing a Gaussian noise generator in verilog,

the code work fine when the output is a vector of logic (16 bit)

but i need this code to communicate with another block which is using Real inputs

i had tryed the $bitstoreal function but it is not working, the output is always O

what i had done is replacing output [16, 0] data_out1 by output real data_out1 in module in/out declaration, and add "assign data_out1 = $bitstoreal(data_out);" data_out is a bit vector coming from an other module

any help

Please could you post the code you have tried so far. – Matthew Taylor May 20 '16 at 08:39 — Matthew Taylor, May 20 '16 at 08:39

score -1 · Answer 1 · answered May 19 '16 at 22:39

-1

data_out should be [15,0] to be 16 bits

answered May 19 '16 at 22:39

DukeDidntNukeEm

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[15,0] is not a range in Verilog/SystemVerilog; use a column: ` [15:0]` – Greg May 19 '16 at 22:54

gaussian noise in systemVerilog

1 Answers1