VHDL can't determine definition of operator "+"

Question

When I am trying to compile my code it has an error in the following part:

overflow <= input_a(15) + input_b(15);

I had declared the input_a and input_b as 15 bit vectors and the libraries that I am using are :

library ieee; 
use ieee.std_logic_1164.all;

So the error is :

Error (10327): VHDL error at alu16.vhd(45): can't determine definition of operator ""+"" -- found 0 possible definitions

Thanks in advance

A couple of us responded to your last question. Did you see that? — Matthew Taylor, May 19 '16 at 17:46

score 5 · Answer 1 · answered May 19 '16 at 18:32

5

If input_a and input_b are std_logic_vector, then input_a(15) and input_b(15) are std_logic, but VHDL does not have a + operator defined for std_logic, thus the error.

If you want to generate a result based on two std_logic values, you have the standard logical operators as and, or, xor, and not available, which will suffice.

answered May 19 '16 at 18:32

Morten Zilmer

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Is there any other way to do what I am trying to do here ? – May 19 '16 at 19:15
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@N.Pipis There are two ways to generate overflow. If you have access to the carry in and the carry out for the MSB you can XOR them. See [Calculating Overflow Flag: Method 2](http://teaching.idallen.com/dat2343/10f/notes/040_overflow.txt). The idea is predicated on you using carry in/out in full adders, in your [Making a 16-bit ALU using 1-bit ALUs - Stack Overflow](https://stackoverflow.com/questions/37274666/making-a-16-bit-alu-using-1-bit-alus) as Matthew indicated or see Calculating Overflow Flag: Method 1 for the other way. Simply adding the MSBs of a and b isn't sufficient. – May 19 '16 at 21:40

score 2 · Answer 2 · answered Jul 27 '21 at 13:30

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Try including the unsigned library...it worked for me! I have the libraries listed and I could did the sum

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

answered Jul 27 '21 at 13:30

guigenta

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score 1 · Answer 3 · edited Mar 13 '18 at 14:26

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If you want to perform arithmetic operations you should declare signed/unsigned signals instead of bit_vector/std_logic_vector.

Those last types can only be used with logical operations such as and/or ... because the compiler doesn't know whether you want your signal to be signed or unsigned.

When using signed/unsigned types you have to use the IEEE numeric_std package.

edited Mar 13 '18 at 14:26

JHBonarius

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answered May 19 '16 at 18:24

A. Kieffer

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score -1 · Answer 4 · answered Mar 13 '18 at 13:11

-1

Add this : use ieee.std_logic_unsigned.all; so you can use the operations + - ... with std_logic

answered Mar 13 '18 at 13:11

Ala

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No, that package should be avoided , [as they were deprecated many many years ago](http://insights.sigasi.com/tech/deprecated-ieee-libraries.html). With VHDL-2008, `numeric_std_unsigned` was introduced, if you REALLY want to do arithmetic using `std_logic_vector`. But better not to. – JHBonarius Mar 13 '18 at 14:25

VHDL can't determine definition of operator "+"

4 Answers4