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I am doing a project that includes writing a makefile. Here I have 2 different makefiles. The first one does the initial build step. In the second makefile I am trying to use the initially generated object files (paths provided) and add one more additional object file generated else where. The problem I am facing here is that the linker is unable to link this new object file to the older ones.

I am using this command to do this step.

arm-none-eabi-g++ -T ../linker.ld -nostartfiles -Xlinker --gc-sections -Wl,-Map,"map_file.map" -specs=nano.specs -o "target.elf" new_file.o all_older_files.o

Here the new_file.o is of arm_eabi version 0 and all_older_files.o is arm_eabi version 5. However, this is not giving me any error or warning. And, interesting thing is that, some of the symbols in the new_file.o are being included in the target.elf file. I have checked and checked the linker script but unable to find a solution and also, check if the eabi version is making some difference, but it is the same if I manually edit the elf file using an elf editor.

All I want is that I need to include the sections in the new_file.o in this target.elf so that I can make use of these.

Pooya
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codelock
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  • First of all, why do you need two makefiles here? You are not, God forbid, calling recursively Make on one makefile from the other? – Mark Galeck May 01 '16 at 13:06
  • I'm confused - you're saying that the linker gives no errors, successfully generates an output ELF, and said linked ELF contains stuff from the input objects - in what way is that "unable to link", exactly? It sounds more like your linker script is simply discarding more than you wanted it to, but without knowing what the script does and what sections the objects actually contain who can say? Or perhaps the 'missing' sections simply weren't referenced by anything else, so it threw them away _because you told it to_. And what does any of this have to do with makefiles? – Notlikethat May 02 '16 at 00:02
  • @MarkGaleck In my project, the first make file is like an auto-gen makefile from the eclipse, since I am using the eclipse IDE based C project. The second makefile is what is set in the Post_Build options and I use for generating some additional files I needed in my project. I didn't want to edit the autogen file or make modifications to the project setting. – codelock May 02 '16 at 06:23
  • @Notlikethat I kindof looking at the same scenario. So, you said the linker is throwing away the sections that weren't referenced. Can you please eloberate. Also, did I tell the makefile to do so? At which point is that happening. Sry if this is a very basic questions, this is the first ever time I am working on makefile and linker scripts. The title may not so appropriate, sry for that.. Thanks a ton for responding... for all! – codelock May 02 '16 at 06:26

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I think I got this. Thank you @Notlikethat, your insight helped me. I figured out that the "--gc-sections" is ignoring the symbols and sections that weren't referenced.

However, when I tried this the first time, the sections were off by large memory portions than it should be and thought this wasn't the solution. But, later I have noticed that the initial auto-gen makefile is also doing the same removing unused sections. So I had to disable that in eclipse project setting and then remove this flag in my makefile as well. This placed the sections where it should be.

Thank you so much, this has saved me tons of time as I was fighting with this for a little longer than needed.

codelock
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