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I am using Xilinx IDE. My ALU module is as follows:

module ALU(in1,in2,operation,clk,out     
);
     input [15:0] in1;
     input [15:0] in2;
     input [3:0] operation;
     input clk;
     output[15:0] out;
reg [15:0] out;
always@(posedge clk)
begin
    case(operation)
                4'b0010:
                    out <= in1+in2;
                4'b0011:
                    out <= in1-in2;
                4'b0100:
                   out <= !in1;
                4'b0101:
                    out <= in1<<in2;
                4'b0110:
                   out <= in1>>in2;
                4'b0111:
                    out <= in1&in2;
                4'b1000:
                    out <= in1|in2;     
                //4'b1001:
                //   out = in1>=in2?16'd0:16'd1;
                default: out <= 16'hFFFF;
    endcase
end
endmodule

My testbench is as follows

module test_projectALU;
reg [15:0] in1;
reg [15:0] in2;
reg [3:0] operation;
reg [15:0] out;
reg clk;

ALU PA(in1,in2,operation,out);
initial
begin
operation=4'b0000;
in1=4'b0000;
in2=4'b0000;
clk = 0;
end
always
begin
    #2 operation=4'b0010; in1=4'b0011; in2=4'b0000;
    #2 operation=4'b0011; in1=4'b0001; in2=4'b0011;
    #2 operation=4'b0000; in1=4'b1100; in2=4'b1101;
    #2 operation=4'b0011; in1=4'b1100; in2=4'b1101;
end
always
begin
    #5 clk=~clk; 
    end

initial $monitor($time,"f=%b, a=%b, b=%b,c=%b",operation,in1,in2,out);
//initial #10 $stop;
endmodule

enter image description here

My output for simulation is attached as image.

Why is that the output is not defined (X state) ? What am I doing wrong?

toolic
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AAI
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2 Answers2

3

out in your testbench is X because it is never assigned a value. You mistakenly connected it to the clk port of the ALU module instance. My simulator gives me a warning:

ALU PA(in1,in2,operation,out);
     |
ncelab: *W,CUVWSP (./tb.v,41|5): 1 output port was not connected: out

Change:

ALU PA(in1,in2,operation,out);

to:

ALU PA(in1,in2,operation,clk,out);

Using connections-by-name instead of connections-by-position can help avoid this type of common error:

ALU PA (
        // Inputs:
    .clk        (clk),
    .in1        (in1),
    .in2        (in2),
    .operation  (operation),
        // Outputs:
    .out        (out)
);
toolic
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0

ALU is an output port, so convert reg to wire before out in your testbench. Since you have taken variables with the same naming write module declaration as: ALU PA(in1, in2, operation, clk, out);

user12299393
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