8 bit error tolerant adder in vhdl .I have tried the codes available but they do not seem to work

Question

"Unsigned 8-bit Error Tolerant Adder" to add two 8-bit numbers in "vhdl code". I have already tried the code below.It gives these errors ** Error: C:/Modeltech_pe_edu_10.4a/examples/etl1.vhd(34): near "Signal": syntax error ** Error: C:/Modeltech_pe_edu_10.4a/examples/etl1.vhd(41): near "EOF": syntax error

#

code below

enter code here

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity adr is
port (a,b: in std_logic_vector(7 downto 0);
  output : out std_logic_vector(7 downto 0));
 end adr ;

architecture eta of adr is
 signal hn,ln: std_logic_vector(7 downto 0);
 signal parta2,partb2,hno:std_logic_vector(3 downto 0);
 signal parta1,partb1: std_logic_vector(3 downto 0);
 signal lno:std_logic_vector(3 downto 0);

begin

process (a,b)

begin

     parta1<= a(7 downto 4); -- parta1<= a(7 downto 4);
     parta2<= a(3 downto 0);  --parta2<= a(3 downto 0);

     partb1<=  b(7 downto 4); --partb1<= b(7 downto 4);
     partb2<=  b(3 downto 0); -- partb2<= b(3 downto 0);




hno<= std_logic_vector(unsigned(parta1)+ unsigned(partb1)); --4 bit msb
lno<= std_logic_vector((unsigned(partb2))xor(unsigned(partb2)));--4bit lsb

Signal hn: std_logic_vector(7 downto 0) := hno(3 downto 0) & B"0000";-- concatenation of hn with zeros
Signal ln: std_logic_vector(7 downto 0) := B"0000" & lno(3 downto 0);--concatenation ln with zeros


output<=(hn or ln);

end process ;

.Thanks in Advance..

Answer 1

OK, you have three issues preventing this from compiling:

Signal hn: std_logic_vector(7 downto 0) := hno(3 downto 0) & B"0000";

In this line, you have already declared hn, and are trying to declare it again here. You can only declare a signal in the declarative region where most of your signals are defined. The second error is the B"0000"; I suspect you are trying to specify that your literal "0000" is binary, but this is the default when assigning to an std_logic_vector anyway. Your correct line would be:

hn <= hno(3 downto 0) & "0000";

The same errors are present in the line below this one.

The third error is pretty trivial. You have remembered an end process;, but forgotten the end architecture;.