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I am currently doing a project in VHDL in which I have a counter that needs to be updated in 100ms or in 1000 ms if a Key is pressed.

Example:

If Key3=0 then
 c=c+1 (100ms)
elsif key3=1 then
 c=c+1 (1000ms)

I'd like to know how to do it in VHDL.

I Believe I should use a process(clock, Key3) but I am not sure how to make the counter increase based on the period.

thanks in advance !

Gabriel
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2 Answers2

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I think you are part way there:

I Believe I should use a process(clock, Key3) but I am not sure how to make the counter increase based on the period.

Think of the problem as a digital design problem, not a coding problem. What would you use to measure the passage of time with in a real digital system? From there use that as a reference to determine whether 100ms or 1000ms have passed.

And once you can measure time, how do you determine how long a particular event is in process?

PlayDough
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If c is a variable (in a process) of type time then

if some_condition then 
   c := c + 100 ms;
else
   c := c + 1000 ms;
end if;

is valid VHDL, and will work in simulation, though time is not very well supported for synthesis.

The easiest solution is for C to count in time steps - such as multiples of clock cycles, and to add 1 or 10 of these.

For example if you have a 10MHz clock:

constant Clock_Period : time := 100 ns;

constant ms_100 : natural := 100 ms / Clock_Period;
constant ms_1000 : natural := 1000 ms / Clock_Period;
signal c : natural;
...

    if some_condition then 
       c <= c + ms_100;
    else
       c := c + ms_1000;
    end if;

And if you change the clock frequency, adjust the clock_period declaration to match.

  • We recently ran into an issue with Vivado regarding the generation of constants and ranges based upon `time` types. As you have described above, this optimizes completely away to nothing. And Xilinx acknowledges that objects of type `time` are not supported. See AR57964 (http://www.xilinx.com/support/answers/57964.html) – PlayDough May 05 '16 at 05:10
  • @PlayDough the AR you linked indicates that type Time IS supported in Vivado, but poorly. As such, this technique is "not recommended" by Xilinx for Vivado users (perhaps they use 32 bit arithmetic when others use 64 bit???) and Synplicity has other issues. But expressing code most clearly at the highest level should be the normal practice; deviatiing from it where tool support is inadequate. –  May 05 '16 at 09:12
  • Fair enough. Time is supported--poorly. But we are limited by the tools we use, as you point out. What we do instead is something like: `constant Clock_Period : real := 100.0e-9;` Real values are supported just fine. – PlayDough May 05 '16 at 15:06
  • @PlayDough : Forgot to say, thanks for reporting the issue with Vivado, that's valuable information. It's also possible (likely?) that mixing Time with Real works correctly, while Time and Integer run into 32-bit (counting in femtoseconds!) limitations. But I haven't tested... –  May 05 '16 at 15:58