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As we know atomic actions cannot be interleaved, so they can be used without fear of thread interference. For example, in a 32-bit OS "x = 3" is considered as an atomic operation "generally" but memory access mostly takes more than one clock cycles, let's say 3 cycles. So here is the case;

Assuming we have multiple parallel data & address buses and thread A tries to set "x = 3", isn't there any chance for another thread, lets say thread B, to access the same memory location in the second cycle ( while thread A in the middle of the write operation ). How the atomicity is gonna be preserved ?

Hope I was able to be clear.

Thanks

stdout
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1 Answers1

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There is no problem with simple assignments at all provided a write performed in a single bus transaction. Even when memory write transaction takes 3 cycles then there are specific arrangements in place that prevent simultaneous bus access from different cores.

The problems arise when you do read-modify-write operations as these involve (at least) two bus transactions and thus such operations could lead to race conditions between cores (threads). These cases are solved by specific opcodes(prefixes) that assert bus lock signal for the whole duration of the next coming instruction or special instructions that do the whole job

Serge
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  • Hi. I know the race condition stuff, but thanks anyways. I actually and particularly wondered what's the "specific arrangements" part when you have parallel buses ( not a single ) that can operate at the same time with or without multiple cores. – stdout Apr 25 '16 at 12:54
  • When you have parallel buses and, say multiport RAM, then it is duty of RAM to handle 'collisions' of single transactions. All other aspects remains the same: the bus lock signal/bus master arbitration/what ever. – Serge Apr 26 '16 at 14:22