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As part of a lecture series on verilog HDL for FPGA programming I have been given this piece of code to create a signed 8-bit greater-than comparator. I have simulated this in xillinx ISE and it shows that the syntax is correct. However I do not understand the begin:comparison line. I understand that in the procedural @always(*) block a begin and end statement is needed, however, in this case when the :comparison is removed the module no longer compiles.

My best guess would be that the :comparison is referring to the sgt = intA > int B; line however I cant understand why or find much information about begin and end statements in that form.

module sgtc(input [7:0] a,b, output reg sgt);
always@(*) begin:comparison

   integer intA, intB;
   intA = a;
   intB = b;
   sgt = intA > intB;

end

endmodule
Qiu
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andowt
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1 Answers1

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comparison is just the name of the block. The author of the code could have called it anything legal. However, in Verilog, you had to name a block if you wanted to declare a variable inside it, which is exactly what you are doing:

integer intA, intB;

So, when you removed the name, this becomes illegal Verilog, which is why it won't compile (in a Verilog-only compiler).

The restriction of having to name a block if you declare a variable inside it is lifted in System-Verilog. So, if you use a compiler that understands this aspect of System-Verilog, then it will compile.

Matthew Taylor
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  • I wanted to add that if you remove the block name in SystemVerilog, you won't be able to access the variables declared inside the block from outside the named block - they become local to the block. – dave_59 Apr 22 '16 at 22:45