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A load word instruction is immediately followed by a branch instruction(of mips 32).

lw r2, (0)r1;-- I swap registers here as opposed to my previous question
Beq r2, r3, target;

To produce a execution diagram, IF ID EX MEM WB. Now where should the stall be for BEQ

IF ID EX MEM WB
   IF *  *   ID EX

or 

IF ID EX MEM WB
   *  *  IF  ID  EX

I just want to understand if both ways are possible. Also, what hardware manipulation is involved for such stalls?

Zac Uwyo H
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1 Answers1

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In the simple pipeline you show, lw is still being decoded while the next insn is being fetched. The pipeline can't tell that they conflict until they're both decoded.

Think through exactly what your 2nd stall is doing: The CPU delays fetching the next instruction before the current one is even decoded. It doesn't know what either instruction is at this point.

IF ID EX MEM WB     lw
   *  IF ID  EX     beq  // lw isn't even decoded yet, and neither is this one, so no way to tell if they conflict.

re: your update: IF isn't an instruction, it's a pipeline stage.

BTW, the question was much clearer before you removed the pipeline diagrams. You should put them back in, with code formatting (select the text and click the {} icon, or hit ctrl-k.)

Peter Cordes
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  • Thanks, I realized I made quite a few errors in my question. Shouldn't the pipeline tell they conflict after the Instruction Fetch? – Zac Uwyo H Apr 11 '16 at 02:26
  • @ZacUwyoH: It can't tell anything until *both* instructions are decoded. What if the second instruction was `add $r10, $r11, $r12`? It doesn't know that until after the 2nd instruction is decoded. So both the diagrams in the question are wrong, in your current edit. – Peter Cordes Apr 11 '16 at 02:53
  • would two stalls after ID work or what should be the solution? – Zac Uwyo H Apr 11 '16 at 03:06
  • @ZacUwyoH: It's the execute stage of `beq` that has to wait, and it has to wait for the result of the load to be known. Without bypass forwarding, it also has to wait for the `WB` stage of the load, where the result is committed to the register file. In that case, two stalls after after ID but before EX sounds right. – Peter Cordes Apr 11 '16 at 03:28
  • @ZacUwyoH: you can mark this as the accepted answer, with the checkbox under the vote arrows, if this answered your question. – Peter Cordes Apr 11 '16 at 17:41