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is any possibility to reset flip-flop vector to different value than all 0? something like:

PROCESS (clk)
    BEGIN
        IF RISING_EDGE(clk) THEN
            IF rst = '1' THEN
                ff <= INPUT_VALUE;
...

This don't survive synthesis. I want to get the value to ff only when resetting, then I'm changing it - it works as a counter with first value set from input.

Joshua
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scarabeus
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    This should be synthesizable because it looks like a synchronous load. Please give a full example and specify the synthesis tool you are using. – Martin Zabel Apr 09 '16 at 19:10
  • The full process is `code PROCESS (clk) BEGIN IF RISING_EDGE(clk) THEN IF rst = '1' THEN iv_reg <= iv; ELSE IF input_change = '1' THEN iv_reg <= STD_LOGIC_VECTOR( UNSIGNED( iv_reg ) + 1 ); ELSE iv_reg <= iv_reg; END IF; END IF; END IF; END PROCESS; ` Synthesized by XST – scarabeus Apr 10 '16 at 06:37
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    Functionally, it looks perfect. What do you mean by doesn't "survive synthesis"? – Matthew Taylor Apr 10 '16 at 07:51
  • I'd make two changes, though: i) If you use `ELSIF` instead of `ELSE IF` you need one less `END IF` which just neatens things up. ii) you never ever need lines line this in a sequential process: `ELSE iv_reg <= iv_reg;`. It's not wrong, but it is unnecessary, because if you don't assign to `iv_reg` it will remember its previous state - precisely the behaviour you want in a sequential process. See: http://www.edaplayground.com/x/2RDr – Matthew Taylor Apr 10 '16 at 07:54
  • Thanks for advices, when I use it without rest of the design, it works fine. So I add extra signal for loading and it's ok. – scarabeus Apr 11 '16 at 17:20
  • @MatthewTaylor One has to be careful with an `elsif` on a reset condition. Depending upon the synthesizer, it may not infer a preset or clear. Our coding standard requires resets be implemented as a single `if` with an `else`, and all other logic nested in the `else` statement. We have seen synthesizers in the past create priority encoders and other logic on the D input, rather than use the preset or clear available, when using `elsif`. – PlayDough Apr 22 '16 at 22:39
  • @PlayDough Thanks for your comment. That's interesting. So, you're trying to persuade your synthesiser to use a flop with a synchronous reset input and it isn't doing so, right? Which synthesisers are you talking about? – Matthew Taylor Apr 23 '16 at 07:10
  • @MatthewTaylor My experience was initially with Autologic and early version of Ambit. And I saw similar issues with ISE (notably with synchronous sets--despite being available in the technology). The other issue with the if/elsif/else is that you may not make use of both the synchronous set and clear unless ordered properly. – PlayDough Apr 25 '16 at 01:44

2 Answers2

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How about implementing a normal reset and then use load signal to set the counter to something else? This to me would be the standard way.

jarno
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The following is an amusing answer that would actually work:

1) Determine the bit pattern of the value that it should be initialized to.

2) For every bit that should be a 1, put a not gate on that line before and after the flip-flop.

Now the initial state after the reset pin is the state you want.

Joshua
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  • Usually the synthesis tool does such things for you. But that on the side, this is a 2 year old question. I doubt the asker still has his/her problem.. – JHBonarius Sep 08 '18 at 07:13