How can I view my simulation results from Active-HDL in a waveform window?

Question

I extended my testbench scripts with Active-HDL support. Active-HDL behaves mostly like QuestaSim or ModelSim, even the command line arguments are similar.

I have an Active-HDL Student Edition and Active-HDL Lattice Edition from Lattice Diamond 3.7 installed. I'm currently using the latter one, because this version is shipped with a full vsimsa (vsim standalone) environment.

My scripts processes the selected testbench in 3 steps:

1. It creates all necessary VHDL libraries with vlib.exe (alib)
2. It compiles all VHDL source files with vcom.exe (acom)
3. It launches vsimsa.exe with a TCL command:
   asim -lib test arith_prng_tb; run -all; bye

The simulation runs and shows a good output:

VHDL/Verilog/EDIF/SystemC Simulator 10.2.3312.5682.02
(c) 1997-2015 Aldec, Inc. All rights reserved.
VSIMSA: Configuration files: `D:\git\PoC\temp\activehdl\library.cfg', `D:\Lattice\diamond\3.7_x64\active-hdl\BIN\vsimsa.cfg'
 Welcome to VSIMSA!
 This message was printed from `startup.do' macro file.

asim -lib test arith_prng_tb; run -all; bye
VSIM: Selected architecture `tb' of entity `arith_prng_tb' from library `test'.
....
....
KERNEL: ASDB file was created in location D:\git\PoC\temp\activehdl\wave.asdb
========================================
POC TESTBENCH REPORT
========================================
Tests          2
 -1: Default test
  0: Test setup for BITS=8; SEED=0x12

Overall
  Assertions   256
    failed     0
  Processes    3
    active     0
  Runtime      2.6 us
========================================
SIMULATION RESULT = PASSED
========================================
Simulation has finished. There are no more test vectors to simulate.

As one can see, asim creates a wave.asdb file, which can be loaded from the GUI, but it's empty (no signals).

So my questions are:

• How can I trace signals into that waveform database file?
• How can I open this file from command line in the GUI?

Answer 1

trace or log command must be used to specify signals to be logged into the simulation database (note these commands are supported in different situations, depending on how you invoke Active HDL).

For example:

log -ports UUT/*

Traces all ports declared in the UUT design region.

log -mem -rec UUT/*

Traces recursively all signals (including Verilog memories) declared in the UUT design region.

log CLK RST

Traces the CLK and RST signals from the current region

You may need to change your compilation optimization options in order to trace all signals of interest.

To answer your second question, you can use the wave command to add waveforms to the current waveform display.