VHDL: Selection of images using switches

Question

I am currently working with VGA in Vivado on a Basys3 FPGA and I am having some issues. I want to generate different images (test mires). I have a separate .vhd file for each of these images, and a top level file where I would like to use a multiplexer for these images in order to assign each of them to a separate switch. My question is: How do I assign an image to a switch, if the outputs from every .vhd file are the three colour signals RGB?

What I tried is that I named these 3 output signals differently for every image, and assigned them to the final output signal when a switch is on using a case structure. I will paste part of it so you guys can get the idea:

This is the top entity

entity VGAdraw is                                                
Port ( CLK      : in STD_LOGIC;                              
       cntHor   : in integer range 0 to cstHorTotSize - 1;   
       cntVer   : in integer range 0 to cstVerTotSize - 1;   
       SW       : in STD_LOGIC_VECTOR (15 downto 0);         
       LED      : out STD_LOGIC_VECTOR (15 downto 0);        
       RED      : out STD_LOGIC_VECTOR (3 downto 0);         
       GREEN    : out STD_LOGIC_VECTOR (3 downto 0);         
       BLUE     : out STD_LOGIC_VECTOR (3 downto 0)          
     );                                                      
end VGAdraw;

This is one of the images:

signal red5, green5, blue5, red7, green7, blue7: STD_LOGIC_VECTOR (3 downto 0);

component Checkers is                                                       
Port ( CLK      : in STD_LOGIC;                                         
       cntHor   : in integer range 0 to cstHorTotSize - 1; 
       cntVer   : in integer range 0 to cstVerTotSize - 1; 
       red7      : out STD_LOGIC_VECTOR (3 downto 0);    
       green7    : out STD_LOGIC_VECTOR (3 downto 0);     
       blue7     : out STD_LOGIC_VECTOR (3 downto 0)       
     );              
end component;

component Checkers
    port map (CLK => CLK,
              cntHor => cntHor,
              cntVer => cntVer,
              red7 => RED,
              green7 => GREEN,
              blue7 => BLUE
             );

The case structure

process                                                       
begin                                                         
case SW is                                                                     
    when "0000000000100000" => RED <= red7;        
                               GREEN <= green7;           
                               BLUE <= blue7;                    
    when others             => RED <= red5;       
                               GREEN <= green5;           
                               BLUE <= blue5;             
end case;                                         
end process;

The VGADraw is the top entity, in which I have declared each image as a different component. Like the one above. How do I assign each of them to a switch on my FPGA board, so i can change to the image I want by turning on a Switch? I have also tried some 'if generate' statements, with no results. Like in this case, having 16 switches on the Basys3, by turning on sw5, I would like to get the image drawn by the Checkers component.

Thanks for any help.

Since you haven't shown us the declarations for `red1` or the component instantiation for Checkers, any help will only be a wild guess. Like, maybe there isn't a declaration for `red1`? — , Apr 01 '16 at 21:11

Maria · Accepted Answer · 2016-04-02T01:13:39.710

0

Just above the process starts your code should be something like this:

signal red1, blue1, green1, red7, green7, blue7 red5, green5, blue5 : STD_LOCIC_VECTOR(3 downto 0);

In general, when making a Structural design, after finishing with components you should declare the signals you need as given above.

edited Apr 02 '16 at 01:13

answered Apr 02 '16 at 01:03

Maria

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Thank you! I got rid of the error this way, but the program isn't working. I am guessing that the reason for that is, that in the case structure it uses these declared signals, and not the ones from the components, that actually draw something? Isn't there a more elegant way to do the selection? Initially I had named all my color signals from every component the same: red, green, blue. Without the numbering. In this way, is it possible in the case structure to do the selection between the components themselves, rather than between the different color signals? – Levente Rigán Apr 02 '16 at 08:00
Since the problem is gone,, you should accept the answer by clicking on the check mark over there <--- . – Maria Apr 02 '16 at 11:24
In general, when you declare a component, in port map you must use the same "names" for the signals as in component. As for what name should the signals of this component have as inputs/ outputs this is up to you. – Maria Apr 02 '16 at 11:30
I would recommend that you edit your post a little bit and give us the port mapping of at least one image. – Maria Apr 02 '16 at 11:32
Great. Now what's the problem? As for the switch you want to have controlling the images, i am assuming you are using xilinx Ise? If so, you need to create a ucf file. It's easy. Just do it on notepad, and save it as NAME.ucf. I fyou need further help, tell me which FPGA you are using? – Maria Apr 02 '16 at 12:39
I am working on a Basys3 FPGA in Vivado 2015.3 Webpack. I have an .ucf file (.xdc for Vivado). My problem is that I do not know how to write the case structure so that I can control each image with a separate switch. So far I have 8 different images and 16 switches, so I would like to be able to display each image on my monitor, (on at a time) by turning on the switch associated to it (let's say the switches sw0 .. sw7). Using the case structure that I exemplified above, the program runs, even the switches work, but it does not display any of the images. – Levente Rigán Apr 02 '16 at 12:51
In the case structure you have taken into consideration only one image. You need to do this for all of your images. – Maria Apr 02 '16 at 13:20
Well I wrote only one to serve as an example. In my actual program I added them all, in a similar fashion. It compiles now and runs error-free, but none of the images is being displayed.. I don't know why. Must be something with the color signals, maybe? – Levente Rigán Apr 02 '16 at 13:23
Well the declaration is correct. The problem should be found in the way you associate your components. Check the connections. Make sure the right signals go to the right inputs/outputs. – Maria Apr 02 '16 at 13:36
Does the order matter? I mean if i write the case structure before or after the port mapping of the components? – Levente Rigán Apr 02 '16 at 13:42
The case structure should be after the declaration of the components and the port map. – Maria Apr 02 '16 at 13:44

VHDL: Selection of images using switches

1 Answers1